HCSL Clock Buffers

The Silicon Labs HCSL Clock Buffers are low-jitter non-PLL based fanout buffers offering industry-leading flexibility while delivering best-in-class performance.  The family features HCSL output buffers with minimal cross-talk and superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. 

With additive jitter as low as 150-fs RMS, the devices are based on our advanced CMOS technology to fanout 4 clocks from 5 - 250 MHz, with guaranteed low additive jitter, low skew, and low propagation delay variability.  

Features

  • Four differential HCSL outputs
  • Provides signal level translation
  • Loss of Signal (LOS) indicator allows system clock monitoring
  • Output Enable (OEB) pin allows glitchless control of output clocks
  • Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V
  • Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
  • Additive jitter: 150 fs RMS typ
  • Industrial temperature range: -40 to +85 °C

Product Matrix

Status
Devices
Part Number Data Sheet Dev KIt Clock Inputs Clock Outputs Frequency Min Frequency Max (MHz) Output Format(s) Additive Jitter (RMS) (ps) VDD (V) VDDO (V) Package Type Package Size (mm) Universal Buffers Differential Buffers LVCMOS Buffers PCI Express Buffers Zero Delay Buffers Single Ended Input
Si5338-EVB 1 4 5 250 HCSL 0.15 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN24 4x4 No Yes Yes Yes No No
Si5338-EVB 1 4 5 250 HCSL 0.15 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN24 4x4 No Yes Yes Yes No Yes
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