Si5330J HSTL Clock Buffer

Frequency Min (MHz)

Frequency Max (MHz)

The Si5330J is a HSTL 1 : 8 low jitter clock buffer/level translator with pin-selectable output clock signal format and divider selection. The Si5330J features a glitchless switching mux, making it ideal for redundant clocking applications. The Si5330J utilizes Silicon Laboratories' advanced CMOS technology to fanout 8 from 5 to 350 MHz guaranteed low additive jitter, low skew, and low propagation delay variability. The Si5330J features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.

Similar Devices: SI5330J

View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 8

Frequency Min (MHz): 5

Frequency Max (MHz): 350

Additive Jitter (ps): 0.15

Zero Delay Mode: No

Package Type: QFN24

Package Size (mm): 4x4

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