Si5330J HSTL Clock Buffer

Frequency Min (MHz)

Frequency Max (MHz)

The Si5330J is a HSTL 1 : 8 low jitter clock buffer/level translator with pin-selectable output clock signal format and divider selection. The Si5330J features a glitchless switching mux, making it ideal for redundant clocking applications. The Si5330J utilizes Silicon Laboratories' advanced CMOS technology to fanout 8 from 5 to 350 MHz guaranteed low additive jitter, low skew, and low propagation delay variability. The Si5330J features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry.

Similar Devices: SI5330J

View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 8

Frequency Min (MHz): 5

Frequency Max (MHz): 350

Additive Jitter (ps): 0.15

Zero Delay Mode: No

Package Type: QFN24

Package Size (mm): 4x4

Development Tools Type
Si5338 Clock Generator Development Kit Development Kits
Title Version Resource Type
Si5338/35/34/56 ClockBuilder Desktop Software 6.5 Software
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Si5330 Data Sheet 1.2 Data Sheets
1204091B_ClockBuilder Desktop Software v5.0.0 Availability-Silicon_Labs Product Change Notifications (PCN)
1107132 Si5330, Si5334, Si5338, Si5355, Si5356 Shipment Media Change std Product Change Notifications (PCN)
1204051B_Si5330 Datasheet v1.0 availability-Silicon_Labs Bulletin Product Change Notifications (PCN)
1208021 ClockBuilder Desktop Software v5 1 0 Availability Product Change Notifications (PCN)
Si5330J-Bxxxxx-GM IBIS Model 3.2 Software
Si5330J a00223 IBIS Model 3.2 Software
Si533x-EVB Schematics and Layout 1.0 Schematic and Layout Files
AN408: Termination Options for Any-Frequency, Any Output Clock Generators and Clock Buffers 0.5 Application Notes
Si5338-EVB User Guide 1.4 User Guides
171002168-Remove-MSL-Level-from-Si5330-Si5334-Si5355-and-Si5356-Datasheets Product Change Notifications (PCN)
AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices 0.5 Application Notes
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Contact Sales Contact Sales
Loading Results