Si53156 PCIe Clock Buffer

Clock Outputs

Package Type

The Si53156 is a PCI-Express Gen 1/2/3 1 : 6 fanout buffer that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 1 reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings.

Similar Devices: SI53156 SI53159

View Datasheet for all specifications View Datasheet for all specifications View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 6

Frequency Min (MHz): 100

Frequency Max (MHz): 210

Additive Jitter (ps): 0.1

Zero Delay Mode: No

Package Type: QFN32

Package Size (mm): 5x5

Title Version Resource Type
Silicon Labs PCIe Clock Jitter Tool README 1.3 Software
PCIe Clock Jitter Tool Installer 1.3 Software
PB #1604293: Si5315x Si5214x Data Sheet Update Product Change Notifications (PCN)
PB #1511301: Bulletin PCIe ClockGen Buffer Product Change Notifications (PCN)
PCN #1609302: Si52146, Si53156, SL28748x, SL28EBxx, SL28PCIexx – Assembly Site addition (UTL) Product Change Notifications (PCN)
AN636: Si5214x and Si5315x Signal Integrity Tuning to Improve Connectivity 0.1 Application Notes
AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation 0.5 Application Notes
Timing MSL Removal Errata 06.04.13 Errata
SI53156 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
Si53156-A13A PCI-Express Gen 1, Gen 2, & Gen 3 Fanout Buffer 1.0 Data Sheets
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families 0.3 Application Notes
Si53156 Data Sheet: PCI-Express Gen 1, Gen 2, & Gen 3 Fanout Buffer 1.3 Data Sheets
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
TimingSoftwareVersionInfo.xml Software
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
PB-1507013-Si53019-A01AGM-to-update-Pin15-18-descriptions-rev2 Product Change Notifications (PCN)
EOL #1403114: Global Foundries (GFSG) 35um and Last Time Buy (LTB) Product Change Notifications (PCN)
17051960 Relocation of Singapore Test Centre and Order Fullfillment Centre Product Change Notifications (PCN)
PB #1506251: Si53108-A01AGM PB to update PLL BW typ specs Product Change Notifications (PCN)
PB #1410022 Si53302 Si53301 v1.1 datasheet Product Change Notifications (PCN)
EOL #1309161: SL38007 Clock Generator EOL Product Change Notifications (PCN)
PCN1308282 SL15300EZC Double Ground Wire UTACTH Product Change Notifications (PCN)
PCN #1309162: SL38X 20QFN 4x4 Silicon Clocks Assembly Test Site Change UTACTH Product Change Notifications (PCN)
SI53308 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI53312 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
時脈樹設計原則 1.0 White Papers
时钟树设计原则 1.0 White Papers
Clock Tree Design Considerations White Papers
Contact Sales Contact Sales
Loading Results