PCI Express (PCIe) 1 : 19 Fanout/Zero-Delay Buffer Si53019-A02AGM

The Si53019-A02AGM is a 1 : 19 PCIe Fanout/Zero-Delay Buffer, that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 19  reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings.

View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 19

Frequency Min (MHz): 100

Frequency Max (MHz): 133

Additive Jitter (ps): 0.08

Zero Delay Mode: Yes

Package Type: QFN72

Package Size (mm): 10x10

Development Tools Type
PCIe Clock Generators and Buffers Evaluation Kits Development Kits
Title Version Resource Type
PCIe Clock Jitter Tool Installer 2.0 Software
2.0 Software
AN871: Driving Long PCIe Clock Lines 0.2 Application Notes
Si53019-A02A Data Sheet: 19-Output PCIe Gen 3 and QPI Buffer 1.3 Data Sheets
PCI Express Solutions 2 Brochures
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
17042536 Si53019 Si53319 Test Site Addition (KYEC Tongluo) Product Change Notifications (PCN)
PB #1602232: PCIE ZDB Product Change Notifications (PCN)
Si53019-A02A IBIS Model 1.0 Software
AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation 0.5 Application Notes
AN874: Cascading Two Si53112 Buffers 0.1 Application Notes
Si53019-A02AGM CAD/CAE Schematic Footprints and Symbols 1.0 Schematic and Layout Files
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
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