PCI Express (PCIe) Zero-Delay Buffer Si53108

The Si53108 is a 1 : 8 PCIe Fanout/Zero-Delay Buffer, that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 8 reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings.

Similar Devices: SI53106 SI53108

Specifications Summary

Inputs: 1

Outputs: 8

Frequency Min (MHz): 100

Frequency Max (MHz): 133

Additive Jitter (ps): 0.08

Zero Delay Mode: Yes

Package Type: QFN48

Package Size (mm): 6x6

Development Tools	Type
PCIe Clock Generators and Buffers Evaluation Kits	Development Kits
Si53108 Clock Buffer Evaluation Kit	Evaluation Kits

Title	Version	Resource Type
PCIe Clock Jitter Tool Installer	2.0	Software
	2.0	Software
Si53108: DB800ZL 8-Output PCIe Gen3 Buffer/Zero Delay Buffer	1.2	Data Sheets
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families	0.3	Application Notes
AN871: Driving Long PCIe Clock Lines	0.2	Application Notes
Si53108 IBIS Model	1.0	Software
AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation	0.5	Application Notes
AN874: Cascading Two Si53112 Buffers	0.1	Application Notes
Si53108-EVB User's Guide	0.1	User Guides
Si53108 CAD/CAE Schematic Footprints and Symbols	1.0	Schematic and Layout Files
Silicon Labs' Timing Solutions for Altera FPGAs by Application	1.0	Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application		White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs		White Papers
Addressing Timing Challenges in 6G-SDI Applications		White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs		White Papers
When to Use a Clock vs. an Oscillator	1.0	White Papers
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet		Product Change Notifications (PCN)
PCI Express Solutions	2	Brochures
Timing Jitter Primer eBook	2	White Papers
Timing Jitter Tutorial and Measurement Guide (e-book)	1	White Papers
PB #1606031: Inner Box Label Change		Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications	0.1	Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark		Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs		Miscellaneous
Timing Solutions for Marvell		Miscellaneous
Timing Solutions for NXP/Freescale Network Processors		Miscellaneous
Timing Solutions for Broadcom Switches/PHYs		Miscellaneous
Timing Solutions for Cavium Processors		Miscellaneous
Timing Solutions for Intel FPGAs		Miscellaneous
Timing Software Version Information		Software
Timing Product Selector Guide		Brochures

PCI Express (PCIe) Zero-Delay Buffer Si53108

Your File Will Start Downloading Shortly