Si53112 PCIe Zero-Delay Buffer

Package Type

Clock Outputs

The Si53112 is a 1 : 12 PCIe Fanout/Zero-Delay Buffer, that meets all of the performance requirements of the Intel DB1900Z specification. The device is optimized for distributing 12  reference clocks for Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/ Gen 3, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each differential output can be enabled through I2C for maximum flexibility and power savings.

Similar Devices: SI53112 SI53115 SI53119

View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 12

Frequency Min (MHz): 100

Frequency Max (MHz): 133

Additive Jitter (ps): 0.08

Zero Delay Mode: Yes

Package Type: QFN64

Package Size (mm): 9x9

Development Tools Type
PCIe Clock Generators and Buffers Evaluation Kits Development Kits
Si53112 Clock Buffer Evaluation Kit Evaluation Kits
Title Version Resource Type
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families 0.3 Application Notes
AN871: Driving Long PCIe Clock Lines 0.2 Application Notes
AN951: Driving Long Traces on PCIe Backplanes for Simple Evaluation 0.5 Application Notes
AN874: Cascading Two Si53112 Buffers 0.1 Application Notes
Si53112-A03A Data Sheet 1.0 Data Sheets
Si53112:DB1200ZL 12-Output PCIe Gen3 Buffer 1.1 Data Sheets
Si53112-EVB User's Guide 0.1 User Guides
SI53112 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
TimingSoftwareVersionInfo.xml Software
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
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