SSTL Clock Buffers

Silicon Labs SSTL Clock Buffers are  low-jitter non-PLL based fanout buffers and industry-leading flexibility while delivering best-in-class performance with additive jitter as low as 150 fs-rms. The family utilizes Silicon Laboratories' advanced CMOS technology to fanout 8 clocks from 5 - 350 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The family features SSTL output buffers with minimal cross-talk and superior supply noise rejection, simplifying low jitter clock distribution in noisy environments.


  • Eight single-ended SSTL outputs
  • Provides signal level translation
  • Loss of Signal (LOS) indicator allows system clock monitoring
  • Output Enable (OEB) pin allows glitchless control of output clocks
  • Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V
  • Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
  • Additive jitter: 150 fs RMS typ
  • Industrial temperature range:
    • -40 to +85 °C

Product Matrix

Part Number Data Sheet Dev KIt Clock Inputs Clock Outputs Frequency Min Frequency Max Output Format(s) Additive Jitter (RMS) VDD (V) VDDO (V) Package Type Package Size (mm) Universal Buffers Differential Buffers LVCMOS Buffers PCI Express Buffers Zero Delay Buffers
Si5338-EVB 1 8 5 350 SSTL 0.15 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN24 4x4 No Yes Yes Yes No

Evaluate SSTL Buffers

The easiest way to begin development with the Si5330 family is with the Si5338-EVB development kit.

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