SL18861DC TCXO 1 : 3 Low-Jitter Clock Buffer with OE

Description

The SL18861DC is a high performance 3 output clock distribution buffer that makes use of a proprietary low phase noise and low power dissipation circuit design. It can be used in baseband mobile RF applications including WLAN, Bluetooth and DVB-H as an input clock reference. The product is designed to isolate each device driven by their clock outputs to minimize Interference between these devices.

Similar Devices: SL18860DC SL18861DC

View Datasheet for all specifications
Specifications Summary

Inputs: 1

Outputs: 3

Frequency Min (MHz): 10

Frequency Max (MHz): 52

Additive Jitter (ps):

Zero Delay Mode: No

Package Type: TDFN10

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