Si5355 LVCMOS 8 Output Clock Generator

Package Type

Phase Jitter RMS (ps)

The Si5355  LVCMOS Clock Generator supports 8 outputs and has a frequency output between 1 and 200 MHz.

Similar Devices: SI5355

View Datasheet for all specifications
Specifications Summary

Reference Inputs: 1

Clock Outputs: 8

Phase Jitter (ps): 2

Input Frequency Min (MHz): 5

Input Frequency Max (MHz): 200

Output Frequency Min (MHz): 1

Output Frequency Max (MHz): 200

Output Format(s): LVCMOS

Jitter Attenuator: No

PCI Express: No

Package Type: QFN24

Package Size (mm): 4x4

Title Version Resource Type
Si5355 Data Sheet 1.2 Data Sheets
SI5355 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
AN408: Termination Options for Any-Frequency, Any Output Clock Generators and Clock Buffers 0.5 Application Notes
171002168-Remove-MSL-Level-from-Si5330-Si5334-Si5355-and-Si5356-Datasheets Product Change Notifications (PCN)
AN360: Crystal Selection Guide for Si533x and Si5355/56 Devices 0.5 Application Notes
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
CBPro Project File Inspector 1.0 Software
CBPro Project File Inspector README 1.0 Software
17061678-End-Of-Life-Notification-for-Legacy-Timing-Products Product Change Notifications (PCN)
AN428 Jumpstart Software Ver 1.3 1.3 Software
AN491: Power Supply Rejection for Low Jitter Clocks 0.2 Application Notes
AN377: Timing and Synchronization in Broadcast Video 0.1 Application Notes
Selecting the Optimum PCIe Clock Source 1.0 White Papers
Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs 1.0 White Papers
The Pros and Cons of Consolidating Frequency Sources Using Oscillators and Clock Generators 1.0 White Papers
AN428: Jump Start: In-System, Flash-Based Programming for Silicon Labs’ Timing Products 0.6 Application Notes
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Contact Sales Contact Sales
Close
Loading Results