Si5371/5372 and Si5342H/5344H Coherent Optical Clocks
The Silicon Labs coherent optical clocks are purpose-built to address the needs of coherent optical communications applications. Each of the low jitter outputs can be configured as a high speed output (up to 2.75 GHz) or a general clock output (up to 717.5 MHz). The Si5371/5372/5344H/5342H leverages 4th generation DSPLL® technology to clean recovered clocks, DCO mode for coherent DSP control via a fast SPI interface, and integrated MultiSynth fractional synthesis to support eye-diagram monitors, FEC, and MUX/DEMUX clock requirements. Such single-chip integration enables designers to meet the stringent performance, form-factor, and power requirements demanded in 100G/200G/400G line cards and modules.
Features
- Up to 2.75 GHz outputs replace VCSOs and synthesizers
- Si5372/5371
- Grade A - external reference (same as Si5344H/42H)
- Grade J - New integrated reference
- Better acoustic emissions performance
- Smaller board area
- Grade A - external reference (same as Si5344H/42H)
- Ultra-low phase jitter:
- High Speed Integer Mode: ≤ 50 fs-rms typ (1 MHz - 40 MHz)
- Fractional MultiSynth Mode: ≤ 90 fs-rms typ (12 kHz - 20 MHz)
- Digitally selectable loop bandwidth for cleaning recovered clocks
- Digitally controlled oscillator (DCO) with fast SPI interface
- MultiSynth fractional synthesis for any-frequency clock support
- Single-chip solution in a small 7 x 7 mm, QFN44 package or LGA44 (Si5371J or 72J)
- Si5372/5371: 4-inputs, Si5344H/5342H: 2-inputs
- Si5372/5344H: 4-outputs, Si5371/5342H: 2-outputs
Evaluate Coherent Optical Clocks
The easiest way to begin development with the Coherent Optical Clocks family is with an EVB kit. The development kit make it easy to move from ClockBuilder Pro device configuration to hands-on performance evaluation.
Product Matrix
| Part Number | Data Sheet | Dev KIt | Description | Control | Reference Inputs | Clock Outputs | Input Frequency | Output Frequency | Output Format(s) | Phase Jitter (RMS) | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Output Bin | Clock Generators | Jitter Attenuating Clocks | Synchronous Ethernet/1588 | PCI Express Clocks | 4G/LTE Wireless Clocks | Intel x86 Clocks |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|
Si5344H-EVB | 100G/400G coherent optics clock, 4-Output, < 2.7 GHz, jitter attenuator, DCO | I2C/SPI | 2 | 2 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.1 | 1.8; 3.3 | 1.8; 2.5; 3.3 | QFN44 | 7x7 | <= 4 | No | Yes | No | No | No | No | |
|
|
Si5344H-EVB | 100G/400G coherent optics clock, 2-Output, < 2.7 GHz, jitter attenuator, DCO | I2C/SPI | 2 | 4 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.1 | 1.8; 3.3 | 1.8; 2.5; 3.3 | QFN44 | 7x7 | <= 4 | No | Yes | No | No | No | No | |
|
|
Si5372A-A-EVB | External reference 100G/400G/600G coherent optics clock, 4-Input, 2-Output | I2C/SPI | 4 | 2 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.09 | 1.8; 3.3 | 1.8; 2.5; 3.3 | QFN44 | 7x7 | <= 4 | No | Yes | No | No | No | No | |
|
|
Si5372J-A-EVB | Internal reference 100G/400G/600G coherent optics clock, 4-Input, 2-Output | I2C/SPI | 4 | 2 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.09 | 1.8; 3.3 | 1.8; 2.5; 3.3 | LGA44 | 7x7 | <= 4 | No | Yes | No | No | No | No | |
|
|
Si5372A-A-EVB | External reference 100G/400G/600G coherent optics clock, 4-Input, 4-Output | I2C/SPI | 4 | 4 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.09 | 1.8; 3.3 | 1.8; 2.5; 3.3 | QFN44 | 7x7 | <= 4 | No | Yes | No | No | No | No | |
|
|
Si5372J-A-EVB | Internal reference 100G/400G/600G coherent optics clock, 4-Input, 4-Output | I2C/SPI | 4 | 4 | 0.008 750 | 0.0001 2750 | CML, HCSL, LVCMOS, LVDS, LVPECL | 0.09 | 1.8; 3.3 | 1.8; 2.5; 3.3 | LGA44 | 7x7 | <= 4 | No | Yes | No | No | No | No |