High Performance Jitter Attenuator, Jitter Cleaner Si5392E  

Frequency Synthesis Mode

Output Frequency Max (MHz)

Reference Type

The Si5392E 2 output, ultra-high performance jitter attenuator combines fourth-generation DSPLL and MultiSynth™ technologies to enable any-frequency clock generation and jitter attenuation for applications like 56G PAM4 SerDes requiring the highest level of jitter performance. The device has an ultra-low jitter of 69fs and a frequency output range up to 1028 MHz and delivers a 0.07 ps rms phase jitter performance with a 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level. The Si5392E can be quickly and easily configured using ClockBuilder Pro software.

Similar Devices: SI5392E SI5392P

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Specifications Summary

Reference Inputs: 4

Clock Outputs: 2

Phase Jitter (fs): 0.07

Input Frequency Max (MHz): 750

Output Frequency Max (MHz): 1028

Output Format(s): CML; HCSL; LVDS; LVPECL

Jitter Attenuator: Yes

PCI Express: No

Package Type: LGA44

Package Size (mm): 7x7

Reference Type: Internal

Development Tools Type
Si5392E 56G SerDes 1-PLL Jitter Attenuator Evaluation Kit Evaluation Kits

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