Si5315A Jitter Attenuator Clock Multiplier

Output Frequency Max (MHz)

The Si5315A jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 2 input(s), 2 output(s) and has a maximum frequency output of 644 MHz. The Si5315A delivers 0.23 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

Similar Devices: SI5315A SI5315B

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Specifications Summary

Reference Inputs: 2

Clock Outputs: 2

Phase Jitter (ps): 0.23

Input Frequency Min (MHz): 0.008

Input Frequency Max (MHz): 644

Output Frequency Min (MHz): 0.008

Output Frequency Max (MHz): 644

Output Format(s): LVPECL; LVDS; CML; LVCMOS

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN36

Package Size (mm): 6x6


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