Si5325A Jitter Attenuator Clock Multiplier

Output Frequency Max (MHz)

The Si5325A jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 2 input(s), 2 output(s) and has a maximum frequency output of 1417 MHz. The Si5325A delivers 0.6 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

Similar Devices: SI5325A SI5325B SI5325C

View Datasheet for all specifications View Datasheet for all specifications View Datasheet for all specifications
Specifications Summary

Reference Inputs: 2

Clock Outputs: 2

Phase Jitter (ps): 0.6

Input Frequency Min (MHz): 10

Input Frequency Max (MHz): 710

Output Frequency Min (MHz): 0.002

Output Frequency Max (MHz): 1417

Output Format(s): LVPECL; LVDS; CML; LVCMOS

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN36

Package Size (mm): 6x6

Contact Sales Contact Sales
Loading Results