Si5328B Jitter Attenuator Clock Multiplier

Output Frequency Max (MHz)

The Si5328B jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 2 input(s), 2 output(s) and has a maximum frequency output of 808 MHz. The Si5328B delivers 0.3 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

Similar Devices: SI5328B SI5328C

View Datasheet for all specifications View Datasheet for all specifications View Datasheet for all specifications
Specifications Summary

Reference Inputs: 2

Clock Outputs: 2

Phase Jitter (ps): 0.3

Input Frequency Min (MHz): 0.008

Input Frequency Max (MHz): 710

Output Frequency Min (MHz): 0.008

Output Frequency Max (MHz): 808

Output Format(s): LVPECL; LVDS; CML; LVCMOS

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN36

Package Size (mm): 6x6

Title Version Resource Type
Si5328 Data Sheet: ITU-T G.8262 Synchronous Ethernet Jitter-Attenuating Clock Multiplier 1.0 Data Sheets
Si5328 User's Guide 0.1 User Guides
PB # 1409121: MSL2 Rating Si531x Si532x Product Change Notifications (PCN)
PB #1410313: MSL2 Rating Si531x Si532x Addendum Product Change Notifications (PCN)
Si5328 IBIS Models 3.3 Software
Si531x/2x/6x DSPLLsim Software Version 5.1 5.1 Software
AN775: Si5328: Synchronous Ethernet Compliance Test Report 0.1 Application Notes
AN776: Using the Si5328 in ITU G.8262-Compliant Synchronous Ethernet Applications 0.2 Application Notes
SI5328 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
EOL #1512102: Si5310 Si5320 Si5364 EOL LTB Notice General Product Change Notifications (PCN)
Si5364 IBIS 3V3 Diff 1.0 Software
Jitter Calculator Readme File Software
Si5320/21/64 Jitter Simulation Software Software
AN687: A Primer on Jitter, Jitter Measurement and Phase-Locked Loops 0.1 Application Notes
AN513: Jitter Attenuation--Choosing the Right Phase-Locked Loop Bandwidth 0.1 Application Notes
AN377: Timing and Synchronization in Broadcast Video 0.1 Application Notes
AN947: Implementing Zero Delay Mode Using the Si5340/41/42/44/45/80 0.1 Application Notes
AN56: Calculating Total Output Jitter for PLLs 0.3 Application Notes
Si531x/2x/6x 抖动衰减时钟建议晶体列表 0.1 Reference Manuals
Si531x/2x/6x ジッター減衰クロック、推奨される水晶リスト 0.1 Reference Manuals
Si531x/2x/6x Jitter Attenuating Clock Recommended Crystal List 0.1 Reference Manuals
High-Performance Clock Integration Key to 40/100G Networks 1.0 White Papers
180418282-Si5347-46-45-44-42-Data-Sheet-Errata-Product-Rev-B-for-LOS-OOF-Sticky-Bits Product Change Notifications (PCN)
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Contact Sales Contact Sales
Close
Loading Results