Si5376 Jitter Attenuator Clock Multiplier

Loop Bandwidth Max

Loop Bandwidth Max

The Si5376 jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 8 input(s), 8 output(s) and has a maximum frequency output of 808 MHz. The Si5376 delivers 0.4 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

Similar Devices: SI5374 SI5376

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Specifications Summary

Reference Inputs: 8

Clock Outputs: 8

Phase Jitter (ps): 0.4

Input Frequency Min (MHz): 2

Input Frequency Max (MHz): 710

Output Frequency Min (MHz): 0.002

Output Frequency Max (MHz): 808

Output Format(s): LVPECL; LVDS; CML; LVCMOS

Jitter Attenuator: Yes

PCI Express: No

Package Type: BGA80

Package Size (mm): 10x10

Title Version Resource Type
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