Si5348B Network Synchronizer Clock for SyncE, SONET/SDH/PDH, and IEEE 1588

Output Frequency Max (MHz)

The Si5348B is a Network synchronizer and jitter attenuator for Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. Utilizing fourth-generation DSPLL technology, the Si5348B provides any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. No external loop filter components are required and the  PLL bandwidth is digitally programmable to values as low as 0.001 Hz. With phase jitter as low as 0.125 ps RMS, the Si5348B accepts 5 clock inputs ranging from 0.008 - 750 MHz and generates up to 7 clock output frequencies ranging from 0.000001 MHz to 350 MHz. The device has enhanced hitless switching to minimize output phase transients when switching between two different inputs at the same frequency. The Si5348B meets all of the requirements specified by ITU-T G.8262 EEC Options 1 & 2, G.812 Type III & IV, G.813 Option 1, and Telcordia GR-1244 and GR-253 (Stratum 3/3E). When used with external IEEE 1588 stack and servo loop software, the Si5348B meets the requirements of ITU-T G.8273.1 and G.8273.2.

Similar Devices: SI5348A SI5348B

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Specifications Summary

Reference Inputs: 5

Clock Outputs: 7

Phase Jitter (ps): 0.125

Input Frequency Min (MHz): 0.008

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.000001

Output Frequency Max (MHz): 350

Output Format(s): CML; HCSL; LVCMOS; LVDS; LVPECL

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN64

Package Size (mm): 9x9

Development Tools Type
Si5348 Network Synchronizer Clock Development Kit Development Kits
Title Version Resource Type
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UG362: Si5348-E Evaluation Board User's Guide 0.1 User Guides
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Si5348 Rev. D ITU-T G.812 Compliance Report 1.0 Miscellaneous
2.29 Release Notes
AN1170: Holdover Using the Si5348 Network Synchronizer Clock 1.0 Application Notes
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