Si5383A Network Synchronizer Clock for SyncE, SONET/SDH/PDH, and IEEE 1588

Output Frequency Max (MHz)

The Si5383A is a 3-PLL network synchronizer with 1PPS in/out for Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. Utilizing fourth-generation DSPLL technology, the Si5383A provides any-frequency clock generation and jitter attenuation for applications requiring the highest level of jitter performance. No external loop filter components are required and the  PLL bandwidth is digitally programmable to values as low as 0.001 Hz. With phase jitter as low as 0.15 ps RMS, the Si5383A accepts 5 clock inputs ranging from 0.000001 - 750 MHz and generates up to 7 clock output frequencies ranging from 0.000001 MHz to 718.5 MHz. The Si5383A meets all of the requirements specified by ITU-T G.8262 EEC Options 1 & 2, G.812 Type III & IV, G.813 Option 1, and Telcordia GR-1244 and GR-253 (Stratum 3/3E). When used with external IEEE 1588 stack and servo loop software, the Si5383A meets the requirements of ITU-T G.8273.1 and G.8273.2.

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Similar Devices: Si5383A Si5383B

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Specifications Summary

Reference Inputs: 5

Clock Outputs: 7

Phase Jitter (ps): 0.15

Input Frequency Min (MHz): 0.000001

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.000001

Output Frequency Max (MHz): 718.5

Output Format(s): CML; HCSL; LVCMOS; LVDS; LVPECL

Jitter Attenuator: Yes

PCI Express: No

Package Type: LGA56

Package Size (mm): 8x8

Development Tools Type
Si5383/84 Network Synchronizer Clock Development Kit Development Kits

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