Si52111-A2 PCI Express (PCIe) Clock Generator

The Si52111-A2 1 output PCIe Gen1 Clock Generator provides industry-leading jitter performance, compliance with PCI Express (PCIe) Gen 1/2/3 requirements, outstanding frequency flexibility and configurable AC parameters for signal integrity optimization. The Si52111-A2 meets PCIe Gen1,2,3 phase jitter requirements with margin, and is available in industrial temperature range. The use of push-pull HCSL outputs ensures the lowest power consumption, while saving board space and external termination resistors for added BOM consolidation.

View Datasheet for all specifications
Specifications Summary

Reference Inputs: 1

Clock Outputs: 1

Phase Jitter (ps):

Input Frequency Min (MHz):

Input Frequency Max (MHz):

Output Frequency Min (MHz): 100

Output Frequency Max (MHz): 100

Output Format(s): HCSL

Jitter Attenuator: No

PCI Express: Yes

Package Type: TDFN10

Package Size (mm): 3x3

Development Tools Type
PCIe Clock Generators and Buffers Evaluation Kits Development Kits
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Title Version Resource Type
Silicon Labs PCIe Clock Jitter Tool README 1.3 Software
PCIe Clock Jitter Tool Installer 1.3 Software
Si52111-A1/A2 PCI-Express Gen 1 Single Output Clock Generator 1.2 Data Sheets
SI52111-B3_B4 PCIe CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI52111-A1_A2 PCIe CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
SI52111-B5_B6 PCIe CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
Clock Generator Considerations for the Rapidly Growing PCIe Market 1.0 White Papers
Programmable Product Request Form (PPR) 3.0 Miscellaneous
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families 0.3 Application Notes
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
TimingSoftwareVersionInfo.xml Software
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
17061678-End-Of-Life-Notification-for-Legacy-Timing-Products Product Change Notifications (PCN)
EOL #1403114: Global Foundries (GFSG) 35um and Last Time Buy (LTB) Product Change Notifications (PCN)
1211021 12xxxx 48QFN6x6 Assembly Site Change std Product Change Notifications (PCN)
PB #1410022 Si53302 Si53301 v1.1 datasheet Product Change Notifications (PCN)
EOL #1309161: SL38007 Clock Generator EOL Product Change Notifications (PCN)
EOL #1507271 Si50122 Addendum to EOL 1506302 Product Change Notifications (PCN)
PCN1308282 SL15300EZC Double Ground Wire UTACTH Product Change Notifications (PCN)
PCN #1309162: SL38X 20QFN 4x4 Silicon Clocks Assembly Test Site Change UTACTH Product Change Notifications (PCN)
Si52131-A11A PCI-Express Gen1, Gen2, & Gen3 Two Output Clock Generator 1.0 Data Sheets
Si50122-A3/A4 CMEMS PCI-Express Gen 1 & Gen 2 Dual Output Clock Generator 0.7 Data Sheets
Selecting the Optimum PCIe Clock Source 1.0 White Papers
Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs 1.0 White Papers
The Pros and Cons of Consolidating Frequency Sources Using Oscillators and Clock Generators 1.0 White Papers
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