PCI Express (PCIe) 2-Output Clock Generator Si52202-A01

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The Si52202-A01 2-output PCIe Gen1 Clock Generator provides industry-leading jitter performance, compliance with PCI Express (PCIe) Gen 1/2/3/4 requirements, outstanding frequency flexibility and configurable AC parameters for signal integrity optimization. The Si52202-A01 meets PCIe Gen1,2,3,4 phase jitter requirements with margin, and is available in industrial temperature range. The use of push-pull HCSL outputs ensures the lowest power consumption, while saving board space and external termination resistors for added BOM consolidation.

Similar Devices: Si52202-A01 Si52202-A02

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Specifications Summary

Reference Inputs: 1

Clock Outputs: 2

Phase Jitter (ps): 0.4

Input Frequency Min (MHz):

Input Frequency Max (MHz): 100

Output Frequency Min (MHz): 100

Output Frequency Max (MHz): 100

Output Format(s): HCSL

Jitter Attenuator: No

PCI Express: Yes

Package Type: QFN20

Package Size (mm): 3x3

Development Tools Type
Si52204-EVB Clock Evaluation Kit Evaluation Kits
PCIe Clock Generators and Buffers Evaluation Kits Development Kits
Title Version Resource Type
PCIe Clock Jitter Tool Installer 2.0 Software
2.0 Software
AN1104: Making Accurate PCIe Gen 4.0 Clock Jitter Measurements 0.1 Application Notes
AN781: Alternative Output Termination for Si5211x, Si5213x, Si5214x, Si5216x, Si522xx, Si5310x, Si5311x, and Si5315x PCIe Clock Generator and Buffer Families 0.3 Application Notes
AN871: Driving Long PCIe Clock Lines 0.2 Application Notes
Si52212/Si52208/Si52204/Si52202 データ・ 0.7 Data Sheets
Si522xx 数据表 0.7 Data Sheets
UG277: Si52204-EVB User's Guide 2.1 User Guides
AN946: PCI-Express 4.0 Jitter Requirements 0.2 Application Notes
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Si52204 PCIe Sample Files Miscellaneous
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
Si522xx IBIS Model Software
Si52212-08-04-02 Data Sheet 0.7 Data Sheets
Si52202, Si52204 Data Sheet Errata 1.0 Errata
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Si52131-A11A PCI-Express Gen1, Gen2, & Gen3 Two Output Clock Generator 1.0 Data Sheets
Si50122-A3_A4Rev0.7.fm 0.7 Data Sheets
17061678-End-Of-Life-Notification-for-Legacy-Timing-Products Product Change Notifications (PCN)
EOL #1403114: Global Foundries (GFSG) 35um and Last Time Buy (LTB) Product Change Notifications (PCN)
1211021 12xxxx 48QFN6x6 Assembly Site Change std Product Change Notifications (PCN)
PB #1410022 Si53302 Si53301 v1.1 datasheet Product Change Notifications (PCN)
EOL #1309161: SL38007 Clock Generator EOL Product Change Notifications (PCN)
EOL #1507271 Si50122 Addendum to EOL 1506302 Product Change Notifications (PCN)
PCN1308282 SL15300EZC Double Ground Wire UTACTH Product Change Notifications (PCN)
PCN #1309162: SL38X 20QFN 4x4 Silicon Clocks Assembly Test Site Change UTACTH Product Change Notifications (PCN)
Selecting the Optimum PCIe Clock Source 1.0 White Papers
Configurable Tiny Clocks Reduce Space, Power and EMI in Consumer Electronics Designs 1.0 White Papers
The Pros and Cons of Consolidating Frequency Sources Using Oscillators and Clock Generators 1.0 White Papers
PCI Express Solutions 2 Brochures
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