SONET/SDH Clock Generators

The Silicon Labs SONET/SDH clock multiplier and jitter attenuator family provides the industry’s best performance in the smallest footprint. Offering jitter generation of less than 0.3-fs RMS (OC-192/STM-64), these devices outperform discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths, and MTIE-compliant hitless switching.   Based on our DSPLL® technology, these clock ICs provide a fully-integrated PLL, eliminating the need for sensitive external loop filter components and costly VCXOs.

Features

  • Ultra-low jitter clock output with jitter generation as low as 0.3 ps RMS
  • Clock output range from 19 to 2,775 MHz
  • Up to three switchable clock inputs
  • Loss-of-lock indication
  • Digital hold for loss-of-input clock
  • Small footprints
  • FEC scaling
  • Hitless switching
  • Low power consumption

Product Matrix

Devices
Part Number Data Sheet Description Control Reference Inputs Input Frequency (MHz) Output Frequency (MHz) Output Format(s) Phase Jitter (RMS) (ps) VDD (V) VDDO (V) Package Type Package Size (mm) Clock Generators
SONET/SDH Jitter Attenuating Clock Pin 1 19 622 19 622 CML 0.3 3.3 3.3 PBGA63 9x9 No
SONET/SDH Jitter Attenuating Clock Pin 1 19 622 19 2488 CML 0.3 3.3 3.3 PBGA63 9x9 No
SONET/SDH Jitter Attenuating Clock Pin 3 19.44 19.44 19 622 CML 0.3 3.3 3.3 PBGA99 11x11 No
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