Si5320 SONET Jitter Attenuating Clock

Output Frequency Max (MHz)

The Si5320 has a jitter of 0.3 ps RMS (OC-192/STM-64) and is part of the SONET/SDH clock multiplier and jitter attenuator family which provides the industry’s best performance in the smallest footprint. The device outperforms discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths and MTIE-compliant hitless switching. Based on Silicon Labs' DSPLL® technology, this clock provides a fully-integrated PLL eliminating the need for sensitive external loop filter components and costly VCXOs.

Similar Devices: SI5320 SI5321

View Datasheet for all specifications
Specifications Summary

Reference Inputs: 1

Clock Outputs: 1

Phase Jitter (ps): 0.3

Input Frequency Min (MHz): 19

Input Frequency Max (MHz): 622

Output Frequency Min (MHz): 19

Output Frequency Max (MHz): 622

Output Format(s): CML

Jitter Attenuator: Yes

PCI Express: No

Package Type: PBGA63

Package Size (mm): 9x9

Title Version Resource Type
AN59: Optimizing Design and Layout for the Si5318/20/21/64 Clock ICs 1.0 Application Notes
AN256: Integrated Phase Noise 0.4 Application Notes
Si5320 SONET/SDH Precision Clock Multiplier IC 2.5 Data Sheets
Si5320-EVB User Guide 0.4 User Guides
DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper White Papers
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
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