Si5321 SONET Jitter Attenuating Clock

The Si5321 has a jitter of 0.3 ps RMS (OC-192/STM-64) and is part of the SONET/SDH clock multiplier and jitter attenuator family which provides the industry’s best performance in the smallest footprint. The device outperforms discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths and MTIE-compliant hitless switching. Based on Silicon Labs' DSPLL® technology, this clock provides a fully-integrated PLL eliminating the need for sensitive external loop filter components and costly VCXOs.

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Specifications Summary

Reference Inputs: 1

Clock Outputs: 1

Phase Jitter (ps): 0.3

Input Frequency Min (MHz): 19

Input Frequency Max (MHz): 622

Output Frequency Min (MHz): 19

Output Frequency Max (MHz): 2488

Output Format(s): CML

Jitter Attenuator: Yes

PCI Express: No

Package Type: PBGA63

Package Size (mm): 9x9

Development Tools Type
Si5321 Development Kit Development Kits

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