Si5321 SONET Jitter Attenuating Clock

The Si5321 has a jitter of 0.3 ps RMS (OC-192/STM-64) and is part of the SONET/SDH clock multiplier and jitter attenuator family which provides the industry’s best performance in the smallest footprint. The device outperforms discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths and MTIE-compliant hitless switching. Based on Silicon Labs' DSPLL® technology, this clock provides a fully-integrated PLL eliminating the need for sensitive external loop filter components and costly VCXOs.

View Datasheet for all specifications
Specifications Summary

Reference Inputs: 1

Clock Outputs: 1

Phase Jitter (ps): 0.3

Input Frequency Min (MHz): 19

Input Frequency Max (MHz): 622

Output Frequency Min (MHz): 19

Output Frequency Max (MHz): 2488

Output Format(s): CML

Jitter Attenuator: Yes

PCI Express: No

Package Type: PBGA63

Package Size (mm): 9x9

Development Tools Type
Si5321 Development Kit Development Kits
Title Version Resource Type
Si5321 SONET/SDH Precision Clock Multiplier IC 2.5 Data Sheets
Si5321 IBIS 3V3 Diff 1.0 Software
Si5321-EVB User Guide 0.4 User Guides
AN59: Optimizing Design and Layout for the Si5318/20/21/64 Clock ICs 1.0 Application Notes
DSP-driven High-performance Clock Sources Radically Alter System Timing Architectures White Paper White Papers
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Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
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Addressing Timing Challenges in 6G-SDI Applications White Papers
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Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
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Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
Timing Product Selector Guide Brochures
Timing Software Version Information Software
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