Si5341D Ultra Low Jitter Clock Generator with 10 Outputs and Integer Only Frequency Systhesis Modes

Output Frequency Max (MHz)

Frequency Synthesis Mode

The Si5341D ultra low jitter clock generator supports 10 outputs and has a maximum frequency output of 350 MHz. The device provides Integer Only frequency synthesis modes, 4 reference inputs and has a Phase Jitter of 0.09 ps.

Similar Devices: SI5341A SI5341B SI5341C SI5341D

View Datasheet for all specifications
Specifications Summary

Reference Inputs: 4

Clock Outputs: 10

Phase Jitter (ps): 0.09

Input Frequency Min (MHz): 10

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.0001

Output Frequency Max (MHz): 350

Output Format(s): CML; HCSL; LVCMOS; LVDS; LVPECL

Jitter Attenuator: No

PCI Express: No

Package Type: QFN64

Package Size (mm): 9x9

Development Tools Type
Si5341 Clock Generator Development Kit Development Kits
Title Version Resource Type
ClockBuilder Pro Software Installer 2.25 Software
AN905: External References: Optimizing Performance 0.3 Application Notes
UG286: ClockBuilderPro Field Programmer Kit 1.2 User Guides
ClockBuilder Pro README 2.25 Release Notes
AN926: Reading and Writing Registers with SPI and I2C 0.2 Application Notes
AN862: Optimizing Jitter Performance in Next-Generation Internet Infrastructure Systems 1.1 Application Notes
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
Si5341-D-EVB User's Guide 0.9 User Guides
Si5341-D IBIS Model 4.3 Software
Si5341 IBIS Model 4.0 Software
AN887: Si534x and Power Supply Noise 0.1 Application Notes
AN959: DCO Applications with the Si5341/40 0.2 Application Notes
AN876: An Implementation of Spread-Spectrum Clocking Using an MCU with the Si5341/40 Clock Generators 0.1 Application Notes
Si5341, Si5340 Rev D Family Reference Manual 1.1 Reference Manuals
Si5341-40 Errata Revision D 1.0 Errata
Si5341 Schematic Footprint and Symbols 1.0 Schematic and Layout Files
Si5341-D-EVB Schematic and Layout Files Schematic and Layout Files
Si5341D Base Part Addendum B Data Sheet Addendums
170801121-Si5340-41-Stuck-Divider-Errata Product Change Notifications (PCN)
Si5341/40 Rev D Data Sheet: Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock Generator 1.0 Data Sheets
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
Timing Solutions for Xilinx FPGAs Miscellaneous
Timing Solutions for Cavium Processors Miscellaneous
Timing Solutions for Marvell Miscellaneous
Timing Solutions for NXP/Freescale Network Processors Miscellaneous
Timing Solutions for Broadcom Switches/PHYs Miscellaneous
Timing Solutions for Intel FPGAs Miscellaneous
Timing Product Selector Guide Brochures
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
Timing Software Version Information Software
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