Si538x Wireless Jitter Attenuating Clocks

The Silicon Labs Si538x family of wireless clock generators leverages our fourth generation DSPLL® technology to address the form factor, power, and performance requirements demanded by radio area network equipment, such as macrocells, small cells, remote radio heads (RRH), and distributed antenna systems (DAS).  

The unparalleled integration found in the device reduces power and size without compromising the stringent performance and reliability demanded in wireless applications. The Si538x is the industry’s first wireless clock generator capable of replacing discrete high performance VCXO-based clocks with a fully integrated CMOS IC solution. The family includes devices capable of generating both wireless clocks with less than 100 fs typical phase jitter and low-jitter general purpose clocks. Learn more about wireless DSPLL technology.

Features

  • Digital frequency synthesis eliminates external VCXO and analog loop filter components
  • Jitter performance <100fs RMS typ (12 kHZ - 20 MHz)
  • Input frequency range:
    • Differential: 10 MHz – 750 MHz 
    • LVCMOS: 10 MHz – 250 MHz
  • Integrated crystal oscillator
  • 1, 2, and 4 DSPLL options
  • Selectable loop bandwidth
  • Status monitoring: LOL, LOS, OOF
  • In-circuit programmable via SPI and I2C
  • Output frequency range:
    • Wireless DSPLL: 480 kHz - 2.94912 GHz
    • Any-rate DSPLL: 480 kHz - 712.5 MHz

Product Matrix

Devices
Part Number Customize Data Sheet Dev KIt Input Frequency (MHz) Output Frequency (MHz) Output Format(s) Description Control Reference Inputs Phase Jitter (RMS) (ps) VDD (V) VDDO (V) Package Type Package Size (mm) 4G/LTE Wireless Clocks Input Frequency Min (MHz) (MHz) Output Frequency Max (MHz) (MHz)
Customize Si5380-D-EVB 10 750 0.48 1474.56 CML; HCSL; LVCMOS; LVDS; LVPECL Ultra-Low Phase Noise, Wireless Jitter Attenuating Clock Multiplier I2C/SPI 4 0.065 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 Yes 10 750 1474.56
New
Si5381E
Customize Si5381E-E-EVB 0.008 750 0.0001 2949.12 CML; HCSL; LVCMOS; LVDS; LVPECL Ultra-Low Phase Noise, Dual-PLL Wireless Jitter Attenuating Clock Multiplier I2C/SPI 4 0.065 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 Yes 0.008 750 2949.12
New
Si5382E
Customize Si5382E-E-EVB 0.008 750 0.0001 2949.12 CML; HCSL; LVCMOS; LVDS; LVPECL Ultra-Low Phase Noise, Multi-PLL Wireless Jitter Attenuating Clock Multiplier I2C/SPI 4 0.065 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 Yes 0.008 750 2949.12
New
Si5386E
Customize Si5386E-E-EVB 0.008 750 0.0001 2949.12 CML; HCSL; LVCMOS; LVDS; LVPECL Ultra-Low Phase Noise, Wireless Jitter Attenuating Clock Multiplier I2C/SPI 4 0.065 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 Yes 0.008 750 2949.12
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