Si5380A Wireless Jitter Attenuator

The Si5380A is a Ultra-Low Phase Noise, Jitter Attenuating Clock Multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5380A accepts 4 clock inputs ranging from 10 to 750 MHz and generates 12 clock outputs from 0.48 to 1474.56 MHz. Based on Silicon Labs’ 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.

View Datasheet for all specifications View Datasheet for all specifications
Specifications Summary

Reference Inputs: 4

Clock Outputs: 12

Phase Jitter (ps): 0.065

Input Frequency Min (MHz): 10

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.48

Output Frequency Max (MHz): 1474.56

Output Format(s): CML; HCSL; LVCMOS; LVDS; LVPECL

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN64

Package Size (mm): 9x9

Title Version Resource Type
ClockBuilder Pro Software Installer 2.19.3 Software
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
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Addressing Timing Challenges in 6G-SDI Applications White Papers
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Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Silicon Labs' Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
TimingSoftwareVersionInfo.xml Software
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
17051960 Relocation of Singapore Test Centre and Order Fullfillment Centre Product Change Notifications (PCN)
AN1093: Achieving Low Jitter Using an Oscillator Reference with the Si5342-47 Jitter Attenuators 0.1 Application Notes
AN926: Reading and Writing Registers with SPI and I2C for Si534x/8x Devices 0.1 Application Notes
AN1051: Si534x/8x Schematic Review Checklist Application Note 0.1 Application Notes
Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual 1.0 Reference Manuals
Simplifying Radio Access Network Clocking Using DSPLL Technology White Papers
AN1111: DSPLL Input Clock Expander 0.1 Application Notes
AN1111: DSPLL Input Clock Expander 0.1 Example Code
UG286: ClockBuilderPro Field Programmer Kit 1.2 User Guides
CBPro Project File Inspector 1.0 Software
Clocks 4.5G Radio Access Networks Presentation Presentations
ClockBuilder Pro Release Notes 2.19.3 Release Notes
PRCN #1607295: Si5380 RevisionD Product Change Notifications (PCN)
SI5380 BXL model for symbols v1.0 Software
Si5380 IBIS models 3.96 Software
Si5380-D IBIS Model 4.3 Software
AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems 1.0 Application Notes
AN898: Achieving Optimal Jitter Performance Using ClockBuilder Pro's Clock Placement Wizard 0.1 Application Notes
AN1057: Hitless Switching using Si534x/8x Devices 0.1 Application Notes
Si5380 Revision D Reference Manual 1.2 Reference Manuals
Si5380 Rev D Data Sheet: Ultra-Low Phase Noise, 12-output JESD204B Clock Generator 1.0 Data Sheets
Si5380-D-EVB User's Guide 0.9 User Guides
Si5380 Errata Revision D 1.0 Errata
The Pros and Cons of Consolidating Frequency Sources Using Oscillators and Clock Generators 1.0 White Papers
Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks with 4th Generation DSPLL Technology v1.0 White Papers
Si5380-D-EVB Schematic and Layout Files 2.2 Schematic and Layout Files
Si5380A Base Part Addendum B Data Sheet Addendums
Si534x External References; Optimizing Performance -- AN905 0.2 Application Notes
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