Si5382E Wireless Jitter Attenuator


The Si5382E is a Ultra-Low Phase Noise, Jitter Attenuating Clock Multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5382E accepts 4 clock inputs ranging from 0.008 to 750 MHz and generates 12 clock outputs from 0.0001 to 2949.12 MHz. Based on Silicon Labs’ 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.

Similar Devices: SI5381E SI5382E

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Specifications Summary

Reference Inputs: 4

Clock Outputs: 12

Phase Jitter (ps): 0.065

Input Frequency Min (MHz): 0.008

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.0001

Output Frequency Max (MHz): 2949.12


Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN64

Package Size (mm): 9x9

Title Version Resource Type
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2.20 Release Notes
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