Si5386E Wireless Jitter Attenuator

The Si5386E is a Ultra-Low Phase Noise, Jitter Attenuating Clock Multiplier optimized for wireless applications which demand the highest level of integration and phase noise performance with ultra-small form factor and power consumption. The Si5386E accepts 4 clock inputs ranging from 0.008 to 750 MHz and generates 12 clock outputs from 0.0001 to 2949.12 MHz. Based on Silicon Labs’ 4th generation DSPLL technology, the device combines frequency synthesis and jitter attenuation in a highly integrated digital solution that eliminates the need for external VCXO and loop filter components. A low cost, fixed-frequency crystal provides frequency stability for free-run and holdover modes. This all-digital solution provides superior performance that is highly immune to external board disturbances such as power supply noise. Learn more about wireless DSPLL technology.

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Specifications Summary

Reference Inputs: 4

Clock Outputs: 12

Phase Jitter (ps): 0.065

Input Frequency Min (MHz): 0.008

Input Frequency Max (MHz): 750

Output Frequency Min (MHz): 0.0001

Output Frequency Max (MHz): 2949.12

Output Format(s): CML; HCSL; LVCMOS; LVDS; LVPECL

Jitter Attenuator: Yes

PCI Express: No

Package Type: QFN64

Package Size (mm): 9x9

Title Version Resource Type
Si5386E-E Schematic Footprint and Symbols Schematic and Layout Files
Si5386E-E-EVB Schematic and Layout Files Schematic and Layout Files
Si5386 Evaluation Board User's Guide 0.1 User Guides
Si5386 Rev E Reference Manual 0.1 Reference Manuals
Si5386 Rev E Data Sheet 0.9 Data Sheets
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
Reducing EMI and Improving Signal Integrity Using Spread Spectrum Clocking 1.0 White Papers
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Silicon Labs' Timing Solutions for Intel FPGAs Miscellaneous
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
TimingSoftwareVersionInfo.xml Software
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
17051960 Relocation of Singapore Test Centre and Order Fullfillment Centre Product Change Notifications (PCN)
AN1093: Achieving Low Jitter Using an Oscillator Reference with the Si5342-47 Jitter Attenuators 0.1 Application Notes
AN926: Reading and Writing Registers with SPI and I2C for Si534x/8x Devices 0.1 Application Notes
AN1051: Si534x/8x Schematic Review Checklist Application Note 0.1 Application Notes
Si534x/8x Jitter Attenuators Recommended Crystal, TCXO and OCXOs Reference Manual 1.0 Reference Manuals
Simplifying Radio Access Network Clocking Using DSPLL Technology White Papers
AN1111: DSPLL Input Clock Expander 0.1 Application Notes
AN1111: DSPLL Input Clock Expander 0.1 Example Code
UG286: ClockBuilderPro Field Programmer Kit 1.2 User Guides
CBPro Project File Inspector 1.0 Software
Clocks 4.5G Radio Access Networks Presentation Presentations
ClockBuilder Pro Release Notes 2.19.3 Release Notes
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