Innovative 4th Generation DSPLL® Technology

Silicon Labs invented its patented DSPLL® technology to simplify the clock multiplication and jitter attenuation circuitry required in high-speed telecommunication applications. This clock technology is now the standard for replacing multiple discrete phase-locked-loop (PLL) components with a single IC that integrates digital signal processing (DSP) circuitry and an ultra-low-jitter voltage-controlled oscillator.

Silicon Labs' proprietary 4th generation DSPLL combines the best of both analog and digital technology. This revolutionary architecture combines an analog low phase noise LC-VCO, a digital PLL architecture and cutting edge CMOS technology to provide a solution that offers higher integration, smaller form factor, lower power and more robust performance in comparison to conventional cascaded PLL devices. These benefits help greatly simplify the design of internet infrastructure equipment, including optical and wired communications, switching, storage and computing systems, as well as in wireless applications such as small cells, pico cells, micro cells, point-point radios and mobile backhaul equipment.

The diagram below highlights the unique architectural innovation behind Silicon Labs' proprietary 4th generation DSPLL architecture to competing cascaded PLL architectures. The DSPLL approach uses a dual-loop PLL architecture with an inner loop and outer loop to realize a low bandwidth jitter attenuating PLL.

For frequency control products, Silicon Lab's proprietary technology eliminates numerous complex manufacturing steps required to frequency tune traditional SAW and crystal-based implementations by moving the frequency synthesis capability into a high-performance, mixed-signal IC. Silicon Labs' XOs and VCXOs derive frequencies up to 1.4 GHz from a simple, low-frequency resonator and calibrate the output to an initial accuracy of 1 ppb. The use of a low-frequency crystal provides tremendous improvements in aging, temperature stability and mechanical reliability.

Additional Resources

DSPLL White Paper

Optimizing Clock Synthesis in Small Cells and Heterogeneous Networks

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DSPLL EVB Software

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CBPro Software

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