Si552 Dual Frequency Low Jitter Voltage Controlled Oscillator (VCXO)

The Si552 is a Dual frequency low jitter voltage controlled oscillator (VCXO) with a typical phase jitter of 0.5 ps that supports frequencies between 10 and 1417 MHz.

View Datasheet for all specifications
Specifications Summary

Minimum Frequency (MHz): 10

Maximum Frequency (MHz): 1417

Selectable Frequencies: Dual

OE (active high):

Output Format(s): CML; CMOS; LVDS; LVPECL

Phase Jitter (ps): 0.5

Stability (+/- ppm): 20; 50; 100

Supply Voltage (V): 1.8; 2.5; 3.3

Temperature Range Min (C): -40

Temperature Range Max (C): 85

Package Size (mm): 5x7

Development Tools Type
Si5xx Single/Dual XO/VCXO Development Kit Development Kits
Title Version Resource Type
AN1035: Timing Solutions for 12G-SDI 0.1 Application Notes
Si552 Data Sheet 1.1 Data Sheets
Si5XX Packing Shipping Improvements Std Product Change Notifications (PCN)
Si520, 53x, 55x, 57x, Crystal Mount Adhesive Change and Die Bond Adhesive Capacity Expansion Std Product Change Notifications (PCN)
Si53x/55x/57x XO/VCXOs Second Source Assembly Site Product Change Notifications (PCN)
PB1309111 XO VCXO Datasheet update Product Change Notifications (PCN)
AN266: VCXO Tuning Slope (Kv), Stability, and Absolute Pull Range (APR) 0.2 Application Notes
AN279: Estimating Period Jitter from Phase Noise 0.1 Application Notes
AN256: Integrated Phase Noise 0.4 Application Notes
AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO 0.2 Application Notes
AN291: Output Buffer Options for Si5xx XO/VCXO Devices 0.3 Application Notes
si5xx5x7-EVB User Guide 0.3 User Guides
Si5xx-EVB User's Guide 0.2 User Guides
552_CMOS_DIFF5x7 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet Product Change Notifications (PCN)
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
TimingSoftwareVersionInfo.xml Software
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark Product Change Notifications (PCN)
PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
EOL #1506302 CMEMS for Si501 2 3 4 and Si50122 Product Change Notifications (PCN)
AN491: Power Supply Rejection for Low Jitter Clocks 0.2 Application Notes
AN377: Timing and Synchronization in Broadcast Video 0.1 Application Notes
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
Timing Solutions for Fox Oscillators 1.0 Miscellaneous
511_DIFF5x7 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Reducing Development Risk in Communications Applications with High-Performance Oscillators White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
UG298: Si5xxUC-EVB 0.2 User Guides
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