Si598 Any Frequency General Purpose Oscillator (XO)

The Si598 is a Any frequency general purpose oscillator (XO) with a typical phase jitter of 0.5 ps that supports frequencies between 10 and 810 MHz.

View Datasheet for all specifications
Specifications Summary

Minimum Frequency (MHz): 10

Maximum Frequency (MHz): 810

Selectable Frequencies: Any

OE (active high): Pin 2

Output Format(s): CML; CMOS; LVDS; LVPECL

Phase Jitter (ps): 0.5

Stability (+/- ppm): 20; 30; 50; 100

Supply Voltage (V): 1.8; 2.5; 3.3

Temperature Range Min (C): -40

Temperature Range Max (C): 85

Package Size (mm): 5x7

Development Tools Type
Si5xx UC Evaluation Kit Development Kits
Title Version Resource Type
Si570/71/98/99 Programmable Oscillator Software 2.0 Software
Si598-99 Data Sheet 1.0 Data Sheets
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AN334: Si57x/598/599 ANSI C Reference Design with Optional Non-Volatile Output Frequency 0.4 Application Notes
AN575: Introduction to FPGA-based ADPLLs 0.1 Application Notes
Si5xx-PROG-EVB User's Guide 0.3 User Guides
Si57x-EVB User Guide 0.2 User Guides
PCI Express Solutions 2 Brochures
Timing Jitter Primer eBook 2 White Papers
Programmable Oscillator Software Comparison White Papers
Timing Jitter Tutorial and Measurement Guide (e-book) 1 White Papers
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PB #1606031: Inner Box Label Change Product Change Notifications (PCN)
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AN765: Thermal Analysis of Silicon Labs Timing Devices 0.1 Application Notes
AN699: FPGA Reference Clock Phase Jitter Specifications 0.1 Application Notes
EOL #1506302 CMEMS for Si501 2 3 4 and Si50122 Product Change Notifications (PCN)
AN491: Power Supply Rejection for Low Jitter Clocks 0.2 Application Notes
AN377: Timing and Synchronization in Broadcast Video 0.1 Application Notes
Silicon Labs' Timing Solutions for Xilinx FPGAs by Application 1.0 Miscellaneous
Silicon Labs' Timing Solutions for Altera FPGAs by Application 1.0 Miscellaneous
Timing Solutions for Fox Oscillators 1.0 Miscellaneous
511_DIFF5x7 CAD/CAE Schematic Footprints and Symbols Schematic and Layout Files
How to Select the Right PLL-based Oscillator for Your Timing Application White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs White Papers
Addressing Timing Challenges in 6G-SDI Applications White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market 1.0 White Papers
Reducing Development Risk in Communications Applications with High-Performance Oscillators White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs White Papers
When to Use a Clock vs an Oscillator 0.1 White Papers
When to Use a Clock vs. an Oscillator 1.0 White Papers
UG298: Si5xxUC-EVB 0.2 User Guides
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