Si547 Quad Frequency Ultra Low Jitter Crystal Oscillator (XO)

The Si547 is a Quad frequency ultra low jitter crystal oscillator (XO) with a typical phase jitter of 0.08 ps that supports frequencies between 0.2 and 1500 MHz.

Specifications Summary

Minimum Frequency (MHz): 0.2

Maximum Frequency (MHz): 1500

Selectable Frequencies: Quad

OE (active high): Pin1 or Pin2

Output Format(s): LVPECL; LVDS; HCSL; CML; CMOS; DUAL CMOS

Phase Jitter (ps): 0.08

Stability (+/- ppm): 25; 50

Supply Voltage (V): 1.8 - 3.3

Temperature Range Min (C): -40

Temperature Range Max (C): 85

Package Size (mm): 3.2x5; 5x7

Development Tools	Type
Si5xx UC Evaluation Kit	Development Kits

Title	Version	Resource Type
Si547 データ・シート	0.71	Data Sheets
Si547 数据表	0.71	Data Sheets
Si547 Data Sheet	0.75	Data Sheets
PB 1601121 Si53019-A01A Package Drawing Update in Data Sheet		Product Change Notifications (PCN)
PCI Express Solutions	2	Brochures
Timing Jitter Primer eBook	2	White Papers
Timing Jitter Tutorial and Measurement Guide (e-book)	1	White Papers
PB #1606031: Inner Box Label Change		Product Change Notifications (PCN)
AN699: FPGA Reference Clock Phase Jitter Specifications	0.1	Application Notes
Timing Solutions for Xilinx FPGAs		Miscellaneous
Timing Solutions for Cavium Processors		Miscellaneous
Timing Solutions for Marvell		Miscellaneous
Timing Solutions for NXP/Freescale Network Processors		Miscellaneous
Timing Solutions for Broadcom Switches/PHYs		Miscellaneous
Timing Solutions for Intel FPGAs		Miscellaneous
Timing Product Selector Guide		Brochures
Timing Software Version Information		Software
Standard Outerbox Label Change to Include RoHS and Halogen Free Mark		Product Change Notifications (PCN)
EOL #1506302 CMEMS for Si501 2 3 4 and Si50122		Product Change Notifications (PCN)
AN491: Power Supply Rejection for Low Jitter Clocks	0.2	Application Notes
AN377: Timing and Synchronization in Broadcast Video	0.1	Application Notes
Silicon Labs' Timing Solutions for Altera FPGAs by Application	1.0	Miscellaneous
Timing Solutions for Fox Oscillators	1.0	Miscellaneous
511_DIFF5x7 CAD/CAE Schematic Footprints and Symbols		Schematic and Layout Files
How to Select the Right PLL-based Oscillator for Your Timing Application		White Papers
DSPLL & MultiSynth Clock Architecture Enables High-Density 10/40/100G Line Card Designs		White Papers
Addressing Timing Challenges in 6G-SDI Applications		White Papers
Timing ICs Keep Beat with Needs of Today’s Embedded Market	1.0	White Papers
Choosing the Optimal Internal or External Clocking Solution for FPGA-Based Designs		White Papers
When to Use a Clock vs an Oscillator	0.1	White Papers
When to Use a Clock vs. an Oscillator	1.0	White Papers
UG298: Si5xxUC-EVB	0.2	User Guides

Si547 Quad Frequency Ultra Low Jitter Crystal Oscillator (XO)

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