Advanced driver assistance systems (ADAS) provide feedback to a human driver and/or assist the driver in performing steering, braking, or acceleration functions in order to increase safety of those in and around the vehicle. ADAS systems span a wide range of functionality in varying degrees of complexity, and are paving the way to fully autonomous vehicles. The Society of Automotive Engineers defines 6 levels of automated driving, ranging from no automation (Level 0) to fully autonomous (Level 5).
Each level of automation provides the vehicle with a higher degree of autonomy to perform driving functions, requiring higher degrees of processing power and data path connectivity to navigate the vehicle using data being collected by sensors in and around the vehicle. As vehicle control shifts from human to the automobile, safety becomes even more important and is one of the most critical elements in ADAS system designs.
ADAS systems span a wide range of applications and complexity in design. Timing requirements will also vary widely, and become increasingly important with each successive level of automation as described above. The jump from Level2 to Level3 requires a significant increase in design complexity and therefore presents new challenges for clock tree design. Adoption of high bandwidth FPGAs and/or processors, high-speed data buses, and 1GbE/10GbE Ethernet connectivity present the need for both differential as well as single-ended clocks, at a mix of varying frequencies, some of which have jitter performance requirements below 500fs RMS to meet the needs of high-speed SerDes and PCIe-Express interfaces. We recommend considering the following when selecting a timing solution for your ADAS design:
Summarize The Clock Tree: Start by outlining all the reference clocks, performance levels, and associated timing features needed within your design. This is commonly known as a clock tree. Each individual design will have its own unique clock tree, but will commonly need a combination of single-ended clocks and differential clocks with different levels of jitter performance requirements. Having this summary will be useful when starting to identify a timing solution.
Reliability: Quartz crystal and oscillator components are mechanical devices that are prone to shock and vibration failure. Even AEC-Q200 rated devices have high FIT rates, oftentimes being the components with the highest point of failure rating in system design. Level3/4/5 ADAS designs often require 8 or more reference clocks. Adding more and more quartz crystal and oscillator components to a system design not only increases the bill of materials and total system cost but also increases reliability concerns as quartz elements are prone to shock and vibration failure. A better approach is to integrate the functionality of that quartz crystal and oscillator components into a clock generator solution, which greatly reduces the FIT rate associated with the timing portion of the design, while also providing numerous other features that can be beneficial to clock tree design, such as spread spectrum for EMI/EMC mitigation, frequency selection, and fault monitoring.
Frequency Flexibility: High bandwidth FPGA and processor platforms require reference clocks of varying frequencies, in both single-ended and differential output output format levels, at different output voltages, all with low jitter requirements. Silicon Labs' patented MultiSynth output divider technology provides 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs while maintaining industry best jitter performance. Each clock output can be individually set to a specific output format level and can be tied to different output voltage levels, easily aligning to your system design requirements.
Safety Compliance: ISO26262 and Automotive Safety Integrity Level (ASIL) compliance are of high importance in ADAS designs or blocks of designs. In these applications, reference clock redundancy and/or health monitoring may be required to meet system-level safety goals. Our AEC-Q100 qualified Si5332 clock generators include fault monitoring and detection features that are not available in quartz crystal or oscillator solutions, such as primary and backup reference inputs for redundancy, input reference health and status monitoring, loss of reference signal fault detection indicators, hardware interface pins to communicate with an ASIL system safety manager IC, and the ability to migrate from a primary input source to secondary input source.
EMI/EMC: Most ADAS clock trees consist of both single-ended and differential reference clocks. Single-ended LVCMOS reference clocks are common sources of emissions in a high-speed digital design and are often a key concern in meeting CISPR25 Class-4 and Class-5 emissions requirements. Silicon Labs provides a unique way to overcome this challenge through the use of complementary LVCMOS output drivers in our AEC-Q100 Si5332 clock generators. By following the recommended design guidelines in AN1237, system designers can mitigate emissions generated by LVCMOS clocks.
Feature Set and Integration: In addition to the safety features and complementary LVCMOS features noted above, our Si5332 clock generators come equipped with many other features that can simplify your design, such as spread spectrum for EMI reduction, frequency selection capability, hardware output enable control and multi-profile selection. Achieving low jitter performance is always a high priority, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board-level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.
PCIe Timing: PCI-Express is a common data bus used in Level3/4/5 ADAS designs, which adds the need for low-jitter differential reference clocks for each PCIe endpoint. Our Si5332 programmable clock generators, Si5225x PCIe Gen1/2/3/4/5 clock generators, and Si5325x PCIe Gen1/2/3/4/5 feature low-power HCSL output drivers with internal termination, with the ability to match either an 85ohm or 100ohm transmission lines without any external termination. Properly measuring jitter on a PCIe reference clock is not straightforward, so to simplify the process and eliminate confusion, we developed the PCIe Clock Jitter Tool. Download the tool for free and learn more about PCIe timing by visiting our PCIe Learning Center.
Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.