AUTOMOTIVE

Infotainment and Digital Cockpit Processing Units

AEC-Q100 qualified timing solutions for infotainment and digital cockpit processing units

overview

Automotive Infotainment and Digital Cockpit Processing Units

Infotainment and digital cockpit processing units provide passenger experience, driver feedback, data processing, and other networking functions.  System architectures are transitioning from a traditional head unit design to a digital cockpit, increasing the need for higher bandwidth processing power, data path connectivity, and interconnect speeds to support audio, video, driver feedback, and other user experience functions.  To meet this challenge, system designers are adopting higher fidelity audio DSPs, PCIe data buses, and higher speed processor platforms.  Some functions may be included that require ASIL rating, so designers must include added levels of functional safety.  As architectures evolve, timing becomes a more critical design consideration.  The number of reference clocks increases, supporting a wide range of both integer and fractional related frequencies, in single-ended and differential formats, all with tighter jitter performance characteristics.   Our AEC-Q100 qualified Si5332 clock generator solutions are ideally suited to provide all single-ended and differential clocks needed in digital cockpit or infotainment system design while providing additional features and functionality not available from standard quartz crystal and oscillator solutions.

Let us help you customize a timing solution to provide all the reference clocks needed for audio DSPs, processors, multi-protocol connectivity, and high-speed PCIe data buses. 

design considerations

Benefits of a silicon-based timing solution

Automotive infotainment system designs have traditionally used quartz crystal and oscillator timing components to satisfy timing requirements. Supporting higher fidelity audio, video, and added functionality requires a greater number of reference clocks, at a mix of varying frequencies, with both differential as well as LVCMOS formats, all with tighter jitter performance requirements.

Selecting an optimal timing solution starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree. Each individual design will have its own unique clock tree, but will commonly need a combination of single-ended clocks and differential clocks. We recommend considering the following when outlining your clock tree and selecting an integrated timing solution:

Reliability: Quartz crystal and oscillator components are mechanical devices that are prone to shock and vibration failure. Even AEC-Q200 rated devices have high FIT rates, oftentimes being the components with the highest point of failure rating in system design. Rather than adding more and more quartz crystal and oscillator components to a system design not only increases the bill of materials and total system cost but also increases reliability concerns as quartz elements are prone to shock and vibration failure. A better approach is to integrate quartz crystal and oscillator components into a clock generator solution. Taking this approach greatly reduces the FIT rate associated with the timing portion of the design, while also providing numerous other features that can be beneficial to clock tree design, such as spread spectrum for EMI/EMC mitigation, frequency selection, and fault monitoring.

Frequency Flexibility: Infotainment and digital cockpit designs often need a combination of different frequencies, with different output format levels, at different output voltages. Silicon Labs' patented MultiSynth output divider technology provides 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs while maintaining industry best jitter performance. Each output can be individually set to a specific output format level, a

Safety Compliance: Some system designs, or blocks of designs, may require a higher degree of safety compliance to meet new Automotive Safety Integrity Level (ASIL) compliance. In these applications, reference clock redundancy and/or health monitoring may be required to meet system-level safety goals. Our Si5332 clock generators feature multiple clock inputs for redundancy, input reference health monitoring, loss of reference signal fault detection indicators, and the ability to migrate from a primary input source to a secondary input source.

EMI/EMC: A combination of single-ended and differential reference clocks to support various different functions are needed. Single-ended LVCMOS reference clocks are common sources of emissions in high-speed digital design and are often a key concern in meeting CISPR Class-4 and Class-5 emissions requirements. Silicon Labs has overcome this challenge by offering a complementary LVCMOS output driver option in our AEC-Q100 clock generators. By following the recommended design guidelines in AN1237, system designers can minimize emissions from LVCMOS clocks and take advantage of all the benefits that a clock generator solution has to offer.

Feature Set and Integration: Silicon Labs’ clock generators come equipped with many features that can simplify your design, such as spread spectrum for EMI reduction on differential PCIe clocks, frequency selection capability on audio clocks, hardware output enable control, multi-profile selection, and redundant clock input capability with fault detection. Achieving low jitter performance is always a high priority, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board-level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.

PCIe Timing: PCI-Express is a common data bus used in infotainment and digital cockpit designs, adding the need for low-jitter differential reference clocks for each PCIe endpoint in system design. Our Si5332 clock generators are capable of providing PCIe Gen1/2/3/4/5 compliant HCSL output clocks, and we also offer stand-alone AEC-Q100 qualified PCIe Gen1/2/3/4/5 clock generators and buffers. These devices feature highly integrated HCSL output drivers that can match 85ohm or 100ohm transmission lines without any external termination, minimizing the PCB area and cost. Properly measuring jitter on a PCIe reference clock is not straightforward, so to simplify the process and eliminate confusion, we developed the PCIe Clock Jitter Tool. Download the tool for free and learn more about PCIe timing by visiting our PCIe Learning Center.

Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.

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