Accelerator cards provide servers with added processing power optimized to handle application specific workloads. Using a standard PCI-Express (PCIe) connector to a server motherboard or backplane, accelerator cards utilize GPUs, FPGAs, or specialized ASICs , which require an array of low jitter reference clocks for PCIe Gen3/4/5 or NVLink data buses, 28G/56G SerDes, and generic system functions. Our broad portfolio of programmable clock generator solutions can be easily customized to consolidate all reference clocks needed in an accelerator card design into a single IC solution to reduce component count, PCB area, and overall system cost.
Selecting the optimal clock generator for an accelerator card starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree. Each accelerator card will have its own unique clock tree, but nearly all of them can be fulfilled using a Silicon Labs' programmable clock generator solution. We recommend considering the following when outlining your clock tree and selecting the ideal clock generator:
Performance: RMS phase jitter is the most important parameter to review before selecting a clock generator. As data rate and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get twice as rigorous, oftentimes cutting system jitter budgets in half. Accelerator cards using PCIe Gen4/5 data buses, as well as an FPGA/SoC/ASIC with 56G/112G SerDes, all of which require reference clocks with <500fs RMS phase jitter. We recommend summarizing your clock tree in order of importance, listing the clocks with the most stringent RMS phase jitter requirements at the top. Silicon Labs’ clock generators are classified by RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.
Frequency Flexibility: Accelerator card designs commonly need a combination of different frequencies, with different output format levels, at different output voltages. Silicon Labs' patented MultiSynth output divider technology provides 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs while maintaining industry best jitter performance. Each output can be individually set to a specific output format level, specific frequency and output voltage level. The frequency at each output does not need to be related to one another.
Feature Set and Integration: Silicon Labs’ clock generators come equipped with many features that can simplify your accelerator card design, such as the spread spectrum for EMI reduction on PCIe clocks, frequency selection capability, output enable control, multi-profile selection, and integrated crystal reference source. We know that jitter performance is very important, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board-level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.
Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.
Availability: Sourcing components on short notice to meet prototype or production builds can be challenging. Our solutions-oriented approach to developing flexible, programmable silicon that can be easily configured using ClockBuilder Pro allows for seamless integration within our manufacturing flow to support pre-programmed samples in less than 2 weeks, and production quantities in as little as 4 weeks. Our field programmer also provides the capability to program blank devices on a moment’s notice, or re-configure a device using I2C.