Data Centers

Flash Array Storage

Flash array storage timing solutions


Timing solutions for PCIe Gen4/5 flash array storage

Data center storage capacity continues to scale with increased workload demand.  Flash array storage appliances present efficiency and scalability advantages over legacy spinning disk systems, particularly for video and AI data intensive workloads, and are continuing to proliferate throughout hyperscale and enterprise data centers.  Migration from SAS/SATA protocols to PCIe/NVMe have provided significant benefits, and present the need for higher precision, lower jitter reference clocks throughout the system design.

design considerations

Optimize your timing solutions for your flash array storage designs

Selecting a timing solution starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree.  Flash array storage systems typically include PCIe/NVME SSD arrays, a storage controller subsystem, and a network switch interfacing directly with the ToR switch or other hardware within the rack.  Each PCB within the overall system presents unique timing requirements, we recommend considering the following when outlining the respective clock trees and selecting the ideal timing solution to implement:

Performance: RMS phase jitter is the most important parameter to review while developing a clock tree. As data rate and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get twice as rigorous, oftentimes cutting system jitter budgets in half. Flash array storage appliances use a combination of PCIe Gen4/5 data buses and high-speed Ethernet connectivity, as well as FPGAs/SoCs/ASICs with 56G/112G SerDes, each of which have unique, low-jitter reference clock timing requirements. We recommend summarizing your clock tree in order of importance, listing the clocks with the most stringent RMS phase jitter requirements at the top. Silicon Labs’ clock generators are classified by RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.

PCIe Timing Basics: The PCIe data bus provides increased bandwidth benefits over traditional SAS/SATA based storage architectures, which are realized using high-speed SerDes technology that requires low-jitter, differential reference clocks.  As a contributing PCI-SIG working group member, Silicon Labs helps to define PCIe reference clock requirements and has been the market leader in delivering next-generation PCIe Gen3/4/5 timing products.  Our products feature highly integrated HCSL output drivers to minimize external components, with RMS phase jitter performance meeting the latest Gen4 and Gen5 specifications with a significant margin.  Properly measuring jitter on a PCIe reference clock is not straightforward, so to simplify the process and eliminate confusion, we developed the PCIe Clock Jitter Tool.  Download the tool for free and learn about PCIe timing by visiting our PCIe Learning Center.  

Frequency Flexibility: Flash array storage controller and switchboard designs commonly need a combination of integer and fractional clock frequencies, with different output format levels, at different output voltages. Silicon Labs' patented MultiSynth output divider technology used in our portfolio of programmable clock generators provide 0ppm synthesis error on up to 12 outputs of varying frequencies while maintaining industry best jitter performance. Learn more about our Si5332 for flash array storage card designs and our Si5391 for switch card designs

Feature Set and Integration:  Silicon Labs’ clock generators come equipped with many value-added features that can simplify your clock tree design, such as spread spectrum for EMI reduction on PCIe clocks, frequency selection capability, output enable control, multi-profile selection, and integrated crystal reference source. We know that jitter performance is of the highest importance, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board-level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.

Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use. The custom part numbers are immediately available for sample or production orders, arriving pre-programmed with the associated configuration file that was developed.

Availability: Sourcing components on short notice to meet prototype or production builds can be challenging. Our solutions-oriented approach to developing flexible, programmable silicon that can be easily configured using ClockBuilder Pro allows for seamless integration within our manufacturing flow to support pre-programmed samples in less than 2 weeks, and production quantities in as little as 4 weeks. Our field programmer also provides the capability to program blank devices on a moment’s notice, or re-configure a device using I2C.

block diagram


ClockBuilder Pro Software

PCIe Clock Jitter Tool

Oscillator Phase Noise Look-Up Tool

Data Center Trends Driving the Next Wave in Timing

Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock Tree

Fast and Easy Measurements with PCIe Clock Jitter Tool

Design Considerations
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