Data Centers

Frequency flexible, low jitter SmartNIC timing solutions

Consolidate entire SmartNIC design clock trees into a single IC solution with our high performance timing solutions.


Integrated clock generators for any SmartNIC design

Upgrades in data center network bandwidth increase network processing overhead on a server processor, reducing the capacity of the server processor to perform its primary functions. SmartNICs combine network processing functionality with traditional NIC functionality, offloading the network processing functions from the server processor, enabling numerous efficiency gains.

Our high-performance timing solutions provide the ideal balance of frequency flexibility and jitter performance, consolidating entire SmartNIC design clock trees into a single IC solution.

design considerations

Identify the right clock generator for your SmartNIC design

Selecting the optimal clock generator for a SmartNIC starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree. Each individual design will have its own unique clock tree but will commonly need a combination of differential and single-ended clocks for Ethernet, PCIe Gen4/5, high speed SerDes, and other system level functions. We recommend considering the following when outlining your clock tree and selecting the ideal clock generator:

Performance: RMS phase jitter is the most important parameter to review before selecting a clock generator. As data rate and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get twice as rigorous, often cutting system jitter budgets in half. SmartNICs use PCIe Gen4/5 data buses, as well as an FPGA/SoC/ASIC with 56G/112G SerDes, all of which require reference clocks with <300fs RMS phase jitter. We recommend summarizing your clock tree in order of importance, listing the clocks with the most stringent RMS phase jitter requirements at the top. Silicon Labs’ clock generators are classified by RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.

Frequency Flexibility: SmartNIC clock trees comprise a combination of different frequencies, with different output format levels, at different output voltages. Silicon Labs' patented MultiSynth output divider technology provides 0ppm synthesis error on both integer and fractional related output frequencies on up to 12 outputs, while maintaining industry best jitter performance. Our Si5332 and Si5341 clock generators provide a balance of frequency flexibility and performance, consolidating entire SmartNIC clock trees into single-IC solutions..

Performance: Many platforms require a mix of PCIe and other high-speed differential clocks with stringent jitter performance requirements. Our Si5332 any-frequency programmable clock generators are capable of synthesizing up to 12 clock outputs, include both PCIe Gen1/2/3/4/5 clocks as well as other frequencies needed within the system design at performance levels below 300fs RMS. Silicon Labs’ clock generators are classified by RMS phase jitter performance level, making it easy to select the right device matching your specific requirements.

Feature Set and Integration: Silicon Labs’ clock generators come equipped with many value added features that can simplify your design, such as dual spread spectrum loops for EMI reduction on PCIe clocks, frequency selection capability, configurable output enable control, multi-profile selection, and integrated crystal reference source. We know that jitter performance is of the highest importance, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.

Customization: Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use.

Availability: Sourcing components on short notice to meet prototype or production builds can be challenging. Our solutions-oriented approach to developing flexible, programmable silicon that can be easily configured using ClockBuilder Pro allows for seamless integration within our manufacturing flow to support pre-programmed samples in less than 2 weeks, and production quantities in as little as 4 weeks. Our field programmer also provides the capability to program blank devices on a moment’s notice, or re-configure a device using I2C.

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ClockBuilder Pro Software

PCIe Clock Jitter Tool

Data Center Trends Driving the Next Wave in Timing

Stop Guessing, Use Silicon Labs Timing Tools to Build Your Clock Tree

Optimize Timing Solutions for High Speed FPGA and Application Processor Designs

Fast and Easy Measurements with PCIe Clock Jitter Tool

FPGA Reference Clock Phase Jitter Specifications

Design Considerations
Block Diagram
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