Adoption of the PCIe interface into solid state drives offers significant advantages over legacy SAS/SATA protocols, the largest of which is the ability to scale. Most data centers today are outfitted with compute and storage hardware using the PCIe Gen3 standard but will quickly migrate to PCIe Gen4 and then to Gen5. Each new generation of the PCIe standard doubles the data rate compared to the previous generation, which puts more strain on the performance specifications of the reference clocks supplied to the SerDes at each endpoint. As the leader in high performance timing solutions, and working group member of the PCI-SIG, Silicon Labs offers the industry's highest performance PCIe Gen3/4/5 clock generators, clock buffers, and programmable clock generators capable of delivering PCIe Gen3/4/5 clocks. Our solutions feature HCSL output drivers with on-chip termination capable of matching either 85ohm or 100ohm transmission lines, reducing the number of external components needed, saving PCB area and system-level cost.
Selecting a timing solution starts with an outline of all the reference clocks, performance levels, and associated timing features needed within the design, commonly known as a clock tree. The type and form factor of SSD usually dictates the type of timing device needed. PCIe buffers, such as the Si53102, are typically used in m.2 form factors where a reference clock is supplied over the connector and needs to be fanned out to multiple endpoints on the SSD. Alternatively, other form factors may need to locally generate PCIe reference clocks on the card, in which case a Si522xx PCIe clock generator is an ideal solution. In some designs, additional clock frequencies may be needed, making our Si5332 or Si5341 programmable clock generators a better choice.
PCIe Timing Basics: The PCIe data bus provides increased bandwidth benefits over traditional SAS/SATA based storage architectures, which are realized using high speed SerDes technology that require low-jitter, differential reference clocks. As a contributing PCI-SIG working group member, Silicon Labs helps to define PCIe reference clock requirements, and has been the market leader in delivering next generation PCIe Gen3/4/5 timing products. Our products feature highly integrated HCSL output drivers to minimize external components, with RMS phase jitter performance meeting the latest Gen4 and Gen5 specifications with significant margin. Properly measuring jitter on a PCIe reference clock is not straightforward, so to simplify the process and eliminate confusion, we developed the PCIe Clock Jitter Tool. Download the tool for free and learn about PCIe timing by visiting our PCIe Learning Center.
Performance: RMS phase jitter is the most important parameter to review while developing a clock tree. As data rate and bandwidth levels increase, the RMS phase jitter requirements on reference clocks get twice as rigorous, often cutting system jitter budgets in half. Maximum jitter specifications on PCIe reference clocks are set by the PCI-SIG and are measured at the endpoint. There are several system architecture considerations that have an impact on the PCIe reference clock jitter specifications. For example, the maximum RMS phase jitter limits are different for systems that choose to employ spread spectrum modulation for EMI reduction, and also whether the design uses a common reference clock or separate reference clock architecture. For more information, please reference AN946. Silicon Labs encompasses all considerations into our datasheet specifications, clearly defining RMS phase jitter performance for all scenarios. Our devices are designed to provide the highest level of margin between actual performance and the maximum allowable limits defined by the PCI-SIG.
Feature Set and Integration: Silicon Labs’ PCIe clock generators and PCIe buffers come equipped with many value added features that help simplify your clock tree design, such as spread spectrum for EMI reduction, hardware output enable pin control, and integrated output termination with a hardware pin that sets the drivers to match either an 85ohm transmission line or 100ohm transmission line. We know that jitter performance is of highest important, so our clock generators include on-chip LDOs on all power pins, resulting in industry best PSNR performance. Suppressing external power supply and board level noise on-chip greatly reduces the number of external components needed for power filtering, reducing board space and cost, and ensures that output clock jitter performance meetings the datasheet specification limits.
Customization: For designs that need a combination of PCIe clocks as well as other frequencies, a programmable clock generator such as our Si5332 is a better solution to consider. Our ClockBuilder Pro software tool guides you through an easy, step-by-step process to generate a configuration file specific to your clock tree requirements. When the configuration file is complete, ClockBuilder Pro can assign a customized part number specific to your design, provide an associated datasheet addendum, and allow you to save it for future use. The custom part numbers are immediately available for sample or production orders, arriving pre-programmed with the associated configuration file that was developed.
Performance Verification: The RMS phase jitter filter masks associated with PCIe reference clocks are non-standard. Standard spectrum analyzers and oscilloscopes do not come equipped with the specific filter masks, making it difficult to accurately measure the jitter on a PCIe clock. Silicon Labs has greatly simplified the process by developing the PCIe Clock Jitter Tool, a user-friendly downloadable software utility that provides step by step guidance to properly measure PCIe reference clock RMS phase jitter adhering to the PCI-SIG documentation. Simply upload a waveform file, select the PCIe Gen settings you wish to measure against, and the tool will perform the calculations providing the results in a clear and concise output format that can be downloaded to a pdf.