About This Webinar
Next-generation reference clock requirements in telecommunications, wireless infrastructure, optical modules, broadcast video, medical imaging and other industrial markets are largely adopting FPGAs, ASICs, and SoCs that use 56G or 112G SerDes to support higher data rates and bandwidth capabilities. There is a direct correlation between SerDes bandwidth increases, and RMS phase jitter requirements on the associated reference clock. As SerDes speed increases, the RMS phase jitter performance needed on the reference clock decreases. In this webinar, David will provide an overview of reference clock requirements on the latest generation of FPGAs, optical DSPs, Coherent DSPs, and network processors. He will highlight the key features from the Si54x Ultra Series XO and VCXO family that ensure reference clock RMS phase jitter performance remain within maximum limits; thus providing system designers added margin in their system jitter budgets.
Speaker
David McParland
Staff Product Manager
Silicon Labs
David McParland is a staff product manager for Silicon Labs’ XO and VCXO product lines, responsible for managing product strategy, new production introductions, and business development. David holds a BSEE and MBA from the University of Texas, and has over 8 years of experience managing frequency control timing products with focus in core/metro telecom, wired communication, optical module, and broadcast audio/video markets.
Duration
45 Minute Presentation
15 Minute Q&A