Clock Buffer Kits & Boards
Devices
Clock Buffers
Select Columns
| Number of Outputs | Output Format(s) | Additive Jitter (ps) | PCIe Compliant | Automotive | |
|---|---|---|---|---|---|
|
Any Format Clock Buffers
Any Format Clock Buffers
|
2, 4, 6, 10 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.05 | ||
|
Automotive Clock Buffers
Automotive Clock Buffers
|
2, 4, 8 | HCSL; LVCMOS; LVDS; LVPECL | 0.1 | ||
|
Automotive PCIe Clock Buffers
PCIe Gen1/2/3/4/5
|
4, 8 | HCSL | 0.05 | ||
|
CMOS Clock Buffers
CMOS Clock Buffers
|
8, 12 | LVCMOS | 0.1, 0.15 | ||
|
HCSL Clock Buffers
HCSL Clock Buffers
|
4 | HCSL | 0.15 | ||
|
HSTL Clock Buffers
HSTL Clock Buffers
|
8 | HSTL | 0.15 | ||
|
LVDS Clock Buffers
LVDS Clock Buffers
|
4, 6, 10 | LVDS | 0.05, 0.15 | ||
|
LVPECL Clock Buffers
LVPECL Clock Buffers
|
2, 4, 5, 6, 10 | LVPECL | 0.05, 0.15 | ||
|
PCIe Clock Buffers
PCIe Clock Buffers
|
2, 4, 6, 8, 9, 12 | HCSL | 0.06, 0.1, 0.2 | ||
|
PCle Zero-Delay Buffers
PCle Zero-Delay Buffers
|
6, 8, 12, 19 | HCSL | 0.08 | ||
|
SSTL Clock Buffers
SSTL Clock Buffers
|
8 | SSTL | 0.15 | ||
|
HSTL Clock Buffers
HSTL Clock Buffers
|
8 | HSTL | 0.15 |
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Kits and Boards
Software and Tools
Clock Buffer Software and Tools
ClockBuilder Pro is a user-friendly software tool that simplifies clock tree design, providing system designers with the ability to customize Silicon Labs’ Clock Generators, Jitter Attenuators, Buffers, and Oscillator products. The tool’s graphical user interface guides users through a step-by-step process to enter the reference clock parameters specific to each design, which results in a configuration file. ClockBuilder Pro also provides users with real time feedback on key performance parameters, offering suggestions to optimize power consumption and RMS phase jitter performance. Once a configuration file is complete, the tool can generate a custom part number and provide a corresponding datasheet addendum. ClockBuilder Pro is also used as the primary interface to communicate with Silicon Labs evaluation boards as well as the Field Programmer Tool.
The PCIe Clock Jitter Tool is designed to simplify the process of taking accurate RMS phase jitter measurements on PCIe Gen 1/2/3/4/5 reference clocks. Users can upload a saved waveform file into the tool, make the necessary selections, and the tool applies the specific filter masks specified by the PCI-SIG to compute the RMS phase jitter. This software takes away all the guesswork of properly measuring PCIe Gen 1/2/3/4/5 common clock and SRIS/SRNS jitter measurements, providing a comprehensive performance report that users can save.
| ClockBuilder Pro Software | ClockBuilder Pro is used to create a customized configuration and part number, and interfaces to all evaluation boards and field programmers. This software is free to download. | |
| PCIe Clock Jitter Tool | The PCIe Clock Jitter Tool is used to quickly and easily take jitter measurements for PCIe Gen1/2/3/4/5 and SRIS/SRNS. This software is free to download. |
Resources
Timing Training
Visit the training portal for informative Timing videos, webinars, and more.
Timing Selector Guide
Selector Guide for all timing products.
PCIe Learning Center
A one-stop page to learn everything about PCI Express.
Timing Community
Visit the Timing community page to ask a question, read articles, and browse application notes and other technical resources.
PCI Express Clock Jitter Tool
The PCIe Clock Jitter Tool is designed to enable users to quickly and easily take jitter measurements for PCIe Gen1/2/3/4/5 and SRNS/SRIS. This software takes away all the guesswork of PCIe Gen1/2/3/4/5 and SRNS/SRIS jitter measurements and margins in board designs. This tool will provide you with accurate results in just a few clicks. This software tool is provided in an executable format to support various common input waveform file, like .csv, .wfm and .bin. The easy-to-use GUI and helpful tips guide users through each step. Release notes and other documentation are also included in the software package.