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Any Format Clock Buffers

Our low jitter clock buffers and level translators (Si533xx) deliver multiple output clock formats from any input clock format. The device flexibility reduces bill of materials complexity by allowing the same product to be used across multiple projects and platforms. Clock formats supported by the low jitter clock buffers and level translators include LVDS, LVPECL, CML, LVCMOS, SSTL, HCSL and HSTL.

Low additive jitter RMS
0.05 ps
Frequency max
Up to 1250 MHz

Any Format Clock Buffer Common Specs

  • Pin-selectable signal format (LVPECL, low-power LVPECL, LVDS, CML, HCSL, LVCMOS)
  • Wide operating frequency DC - 1.25 GHz
  • 2-10 differential or 4-20 LVCMOS outputs
  • Accepts any differential or single-ended input
  • Low additive jitter: 45 fs rms (12 kHz - 20 MHz) typical
  • Glitchless clock switching
  • Synchronous and Individual output enable control options available
  • Integrated voltage level translation
  • Selectable drive strength to tailor jitter/EMI performance
  • Loss of signal (LOS) indicator
  • Optional output clock division: div-1, div-2, div-4
  • Low output-output skew: <50 ps
  • Excellent PSRR
  • Independent VDD and VDDO: 1.8, 2.5 or 3.3 V
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Part Number Number of Inputs Number of Outputs Frequency Min (MHz) Frequency Max Output Format(s) Additive Jitter VDD (V) VDDO (V) Package Type Package Size (mm) Universal Buffers LVCMOS Buffers PCIe Compliant Zero Delay Buffers Dual Automotive
Si53301-B-GM
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2 6 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN32 5x5
Si53302-B-GM
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2 10 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
Si53303-B-GM
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2 10 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
Si53304-B-GM
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2 6 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN32 5x5
Si53305-B-GM
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2 10 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
Si53306-B-GM
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1 4 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN16 3x3
Si53307-B-GM
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2 2 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.5 V; 1.8 V; 2.5 V 1.8 V; 2.5 V; 3.3 V QFN17 3x3
Si53308-B-GM
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2 6 1 725 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN32 5x5
Si53311-B-GM
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2 6 DC 1250 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN32 5x5
Si53312-B-GM
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2 10 DC 1250 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
Si53313-B-GM
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2 10 DC 1250 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
Si53314-B-GM
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2 6 DC 1250 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN32 5x5
Si53315-B-GM
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2 10 DC 1250 CML; HCSL; LVCMOS; LVDS; LVPECL 0.05 1.8 V; 2.5 V; 3.3 V 1.8 V; 2.5 V; 3.3 V QFN44 7x7
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      Si533xx Low Jitter Clock Buffer Evaluation Kit

      The Si53301/4-EVB development kit allows customers to quickly evaluate the performance of Silicon Labs’ Si5330x low jitter fanout buffers. Populated with a Si53301 2-input, 6-output buffer, the EVB can be used to evaluate the performance of all Si533xx products. The device is easily configured via jumpers with no external software required. SMA connections provide easy connection to test equipment.

      Si533xx Low Jitter Clock Buffer Evaluation Kit

      The Si53301/4-EVB development kit allows customers to quickly evaluate the performance of Silicon Labs’ Si5330x low jitter fanout buffers. Populated with a Si53301 2-input, 6-output buffer, the EVB can be used to evaluate the performance of all Si533xx products. The device is easily configured via jumpers with no external software required. SMA connections provide easy connection to test equipment.
      MSRP $149.00
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