HCSL Clock Buffers

Our HCSL clock buffers are low jitter, non-PLL based fanout buffers delivering best-in-class performance, minimal cross-talk, and superior supply noise rejection. Devices are available in industrial and automotive grade2 temperature ranges.

Outputs
4 differential HCSL
Additive jitter
150 fs RMS typ

HCSL Buffer Common Specs

  • Four differential HCSL outputs
  • Provides signal level translation
  • Loss of Signal (LOS) indicator allows system clock monitoring
  • Output Enable (OEB) pin allows glitchless control of output clocks
  • Single core supply with excellent PSRR: 1.8, 2.5, or 3.3 V
  • Automotive Grade2, -40 to +105 °C
  • AECQ-100 qualified options
  • Output driver supply voltage independent of core supply: 1.5, 1.8, 2.5, or 3.3 V
  • Additive jitter: 150 fs RMS typ
  • Industrial temperature range: -40 to +85 °C
Status
Find the Right HCSL Buffer Select Columns
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Part Number Number of Inputs Number of Outputs Frequency Min (MHz) Frequency Max Output Format(s) Additive Jitter VDD (V) VDDO (V) Package Type Package Size (mm) Universal Buffers Differential Buffers LVCMOS Buffers PCIe Compliant Zero Delay Buffers Single Ended Input Automotive
1 4 5 250 HCSL 0.15 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN24 4x4
1 4 5 250 HCSL 0.15 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN24 4x4

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For PCIe applications, please refer to our portfolio of low-power PCIe Gen1/2/3/4/5 fanout buffers that feature HCSL output drivers with internal termination.

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