PCIe Clock Generator Common Specs
- Complete portfolio of PCI Express Gen1/2/3/4/5 clocks and buffers
- Wide range of power supply: 1.5 V, 1.8 V, 2.5 V, 3.3 V
- Push-pull HCSL output buffer technology
- 12-bit Analog to Digital converter (ADC)
- Low power conumption
- Programmable spread spectrum
- Individual hardware pin for output enable and spread spectrum control
- I²C/SMBus programmable
- Supports optional LVPECL, LVDS, or CML levels
- -40 to +85 °C operation
- Small form factor QFN and TDFN packaging
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| Part Number | Reference Inputs | Number of Outputs | Output Frequency | Output Format(s) | Description | Control | Phase Jitter (RMS) | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Clock Generators | Jitter Attenuating Clocks | Synchronous Ethernet/1588 | PCIe Compliant | 4G/LTE Wireless Clocks | Intel x86 Clocks | Spread Spectrum | Jitter Recommended Range (fs) | Line Impedance Match |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 1 | 4 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 4-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 85Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN32 | 5x5 | <= 500 | 85 | ||||||||
| 1 | 12 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 12-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 85Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN64 | 9x9 | <= 500 | 85 | ||||||||
| 1 | 8 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 8-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 100Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN48 | 6x6 | <= 500 | 100 | ||||||||
| 1 | 1 | 100 100 | HCSL | 1-output PCIe Gen 3 clock generator with SS | — | 0.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 1000 | 100 | ||||||||
| 1 | 1 | 100 100 | HCSL | 1-output PCIe Gen 1 clock generator with SS | — | 3.3 | 3.3 | TDFN10 | 3x3 | <=86000 (pk-pk) | 100 | |||||||||
| 1 | 8 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 8-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 85Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN48 | 6x6 | <= 500 | 85 | ||||||||
| 1 | 1 | 100 100 | HCSL | 1-output PCIe Gen 2 clock generator | — | 1.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 3100 | 100 | ||||||||
| 1 | 6 | 100 100 | HSCL | 6-output PCIe Gen 1/2/3 clock generator | I2C/Pin | 1 | 3.3 | 3.3 | QFN32 | 5x5 | <= 600 | 100 | ||||||||
| 1 | 2 | 100 100 | HCSL | 1.5-1.8 V 2-output PCIe Gen 1/2/3/4 clock generator, with 100Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN20 | 3x3 | <= 500 | 100 | ||||||||
| 1 | 4 | 100 100 | HSCL | 4-output PCIe Gen 1/2/3 clock generator | I2C/Pin | 1 | 3.3 | 3.3 | QFN24 | 4x4 | <= 600 | 100 | ||||||||
| 1 | 1 | 100 100 | HCSL | 1-output PCIe Gen 2 clock generator with SS | — | 1.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 3100 | 100 | ||||||||
| 1 | 9 | 100 100 | HSCL | 9-output PCIe Gen 1/2/3 clock generator | I2C/Pin | 1 | 3.3 | 3.3 | QFN48 | 5x5 | <= 600 | 100 | ||||||||
| 0 | 1 | 100 100 | HCSL | 1-output PCIe Gen 1 clock generator | — | 3.3 | 3.3 | TDFN10 | 3x3 | <=86000 (pk-pk) | 100 | |||||||||
| 1 | 2 | 100 100 | HCSL | 1.5-1.8 V 2-output PCIe Gen 1/2/3/4 clock generator, with 85Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN20 | 3x3 | <= 500 | 85 | ||||||||
| 1 | 12 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 12-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 100Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN64 | 9x9 | <= 500 | 100 | ||||||||
| 1 | 2 | 100 100 | HCSL | 2-output PCIe Gen3 clock generator with SS | — | 0.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 1000 | 100 | ||||||||
| 1 | 2 | 25 100 | HSCL; LVCMOS | 2-output PCIe Gen 1/2/3 clock generator with 25 MHz reference | I2C/Pin | 1 | 3.3 | 3.3 | QFN24 | 4x4 | <= 600 | 100 | ||||||||
| 1 | 2 | 100 100 | HCSL | 2-output PCIe Gen1 clock generator | — | 3.3 | 3.3 | TDFN10 | 3x3 | <=86000 (pk-pk) | 100 | |||||||||
| 1 | 5 | 25 100 | HSCL; LVCMOS | 4-output PCIe Gen 1/2/3 clock generator with 25 MHz reference | I2C/Pin | 1 | 3.3 | 3.3 | QFN24 | 4x4 | <= 600 | 100 | ||||||||
| 1 | 2 | 100 100 | HCSL | 2-output PCIe Gen 1 clock generator with SS | — | 3.3 | 3.3 | TDFN10 | 3x3 | <=86000 (pk-pk) | 100 | |||||||||
| 1 | 2 | 100 100 | HCSL | 2-output PCIe Gen 3 clock generator | — | 0.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 1000 | 100 | ||||||||
| 1 | 4 | 25 100 | HCSL; LVCMOS | 1.5-1.8 V 4-output PCIe Gen 1/2/3/4 + 25 MHz LVCMOS clock generator, with 100Ω internal termination | I2C/Pin | 0.4 | 1.5-1.8 | 1.5-1.8 | QFN32 | 5x5 | <= 500 | 100 | ||||||||
| 1 | 2 | 100 100 | HCSL | 2-output PCIe Gen 2 clock generator | — | 1.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 3100 | 100 | ||||||||
| 1 | 1 | 100 100 | HCSL | 1-output PCIe Gen 3 clock generator | — | 0.4 | 3.3 | 3.3 | TDFN10 | 3x3 | <= 1000 | 100 |
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Si52111-B6 PCIe Clock Generator Evaluation Kit
The Si52111-B6-EVB allows you to measure the jitter performance, power consumption, and signal integrity. The boards feature SMA connectors for robust low jitter signal integrity measurements.
Si52111-B6 PCIe Clock Generator Evaluation Kit
The Si52111-B6-EVB allows you to measure the jitter performance, power consumption, and signal integrity. The boards feature SMA connectors for robust low jitter signal integrity measurements.
Featured Tool
PCIe Clock Jitter Tool
Quickly and easily take jitter measurements for PCIe Gen1/2/3/4 and SRNS/SRIS.
