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Clock Jitter Attenuators

Our clock jitter attenuators generate infinite combinations of low jitter output frequencies from any input frequency. Based on our innovative third generation wireless DSPLL® architecture, these devices simplify clock tree design by replacing multiple clocks and oscillators and minimizing bill of materials count and complexity.

Frequency range
2 kHz to 1.4 GHz
Ultra-low jitter
300 fs RMS

Clock Jitter Attenuator Common Specs

  • Generates any frequency on any output (2 kHz to 1.4 GHz)
  • Ultra-low jitter: 300 fs RMS
  • Integrated loop filter with selectable loop bandwidth
  • Hitless switching with phase buildout (auto/manual)
  • Synchronous and freerun modes
  • Best-in-class PSRR
  • Dynamically reconfigurable output frequency (per output)
  • Fast-lock < 100 ms
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Part Number Number of Inputs Number of Outputs Input Frequency Min Input Frequency Max Output Frequency Min Output Frequency Max Output Format(s) Description Phase Jitter (RMS) VDD (V) VDDO (V) Package Type Package Size (mm) Synchronous Ethernet/1588 Intel x86 Clocks
Si5315A
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2 2 0.008 644 0.008 644 LVPECL; LVDS; CML; LVCMOS SyncE/T1/E1 jitter attenuating clock 0.23 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5315B
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2 2 0.008 644 0.008 125 LVPECL; LVDS; CML; LVCMOS SyncE/T1/E1 jitter attenuating clock 0.23 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5316
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2 1 19 710 19 710 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5317A
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1 2 1 711 1 711 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5317B
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1 2 1 350 1 350 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5317C
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1 2 1 200 1 200 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5317D
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1 2 1 100 1 100 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5319A
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1 1 2 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5319B
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1 1 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5319C
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1 1 2 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5322
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2 2 19 707 19 1050 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.6 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5323
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2 2 8 707 0.008 1050 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5324A
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2 2 2 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5324B
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2 2 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5324C
Buy Sample Dev Kit
2 2 2 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5324D
Buy Sample Dev Kit
2 2 2 710 0.002 150 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5325A
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2 2 10 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.6 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5325B
Buy Sample Dev Kit
2 2 10 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.6 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5325C
Buy Sample Dev Kit
2 2 10 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.6 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5326A
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2 2 2 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5326B
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2 2 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5326C
Buy Sample Dev Kit
2 2 2 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5327B
Buy Sample Dev Kit
2 2 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.5 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5327C
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2 2 2 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.5 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5327D
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2 2 2 710 0.002 243 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.5 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5328B
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2 2 0.008 710 0.008 808 LVPECL; LVDS; CML; LVCMOS SyncE jitter attenuating clock 0.3 2.5; 3.3 2.5; 3.3 QFN36 6x6
Si5328C
Buy Sample Dev Kit
2 2 0.008 710 0.008 346 LVPECL; LVDS; CML; LVCMOS SyncE jitter attenuating clock 0.3 2.5; 3.3 2.5; 3.3 QFN36 6x6
Si5365
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4 5 19 707 19 1050 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.6 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN36 6x6
Si5366
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4 5 8 707 0.008 1050 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 TQFP100 14x14
Si5368A
Buy Sample Dev Kit
4 5 2 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 TQFP100 14x14
Si5368B
Buy Sample Dev Kit
4 5 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 TQFP100 14x14
Si5368C
Buy Sample Dev Kit
4 5 2 710 0.002 346 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 TQFP100 14x14
Si5369
Buy Sample Dev Kit
4 5 2 710 0.002 1417 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.3 1.8; 2.5; 3.3 1.8; 2.5; 3.3 TQFP100 14x14
Si5374
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8 8 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.4 1.8; 2.5 1.8; 2.5 BGA80 10x10
Si5375
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4 4 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.4 1.8; 2.5 1.8; 2.5 BGA80 10x10
Si5376
Buy Sample Dev Kit
8 8 2 710 0.002 808 LVPECL; LVDS; CML; LVCMOS Any-frequency jitter attenuating clock 0.4 1.8; 2.5 1.8; 2.5 BGA80 10x10
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      Si5315 Any-Frequency Precision Clock Multiplier/Jitter Attenuator Development Kit

      The Si5315 precision clock accepts dual clock inputs ranging from 8 kHz to 644 MHz and generates dual clock outputs ranging from 8 kHz to 644 MHz. The Si5315 precision clock is based on Silicon Labs' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5315 is ideal for SyncE applications.

      Si5315 Any-Frequency Precision Clock Multiplier/Jitter Attenuator Development Kit

      The Si5315 precision clock accepts dual clock inputs ranging from 8 kHz to 644 MHz and generates dual clock outputs ranging from 8 kHz to 644 MHz. The Si5315 precision clock is based on Silicon Labs' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5315 is ideal for SyncE applications.
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