Clock Jitter Attenuator Common Specs
- Generates any frequency on any output (2 kHz to 1.4 GHz)
- Ultra-low jitter: 300 fs RMS
- Integrated loop filter with selectable loop bandwidth
- Hitless switching with phase buildout (auto/manual)
- Synchronous and freerun modes
- Best-in-class PSRR
- Dynamically reconfigurable output frequency (per output)
- Fast-lock < 100 ms
- Serially programmable via I2C/SPI
- Any format, any output: LVPECL, CML, LVDS, LVCMOS
- In-circuit programmable
- Easy to use Clock Software Development Tools
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| Part Number | Number of Inputs | Number of Outputs | Input Frequency Min | Input Frequency Max | Output Frequency Min | Output Frequency Max | Output Format(s) | Description | Phase Jitter (RMS) | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Synchronous Ethernet/1588 | Intel x86 Clocks |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2 | 2 | 0.008 | 644 | 0.008 | 644 | LVPECL; LVDS; CML; LVCMOS | SyncE/T1/E1 jitter attenuating clock | 0.23 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 0.008 | 644 | 0.008 | 125 | LVPECL; LVDS; CML; LVCMOS | SyncE/T1/E1 jitter attenuating clock | 0.23 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 1 | 19 | 710 | 19 | 710 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 2 | 1 | 711 | 1 | 711 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 2 | 1 | 350 | 1 | 350 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 2 | 1 | 200 | 1 | 200 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 2 | 1 | 100 | 1 | 100 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 1 | 2 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 1 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 1 | 1 | 2 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 19 | 707 | 19 | 1050 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.6 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 8 | 707 | 0.008 | 1050 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 150 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 10 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.6 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 10 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.6 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 10 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.6 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.5 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.5 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 2 | 710 | 0.002 | 243 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.5 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 0.008 | 710 | 0.008 | 808 | LVPECL; LVDS; CML; LVCMOS | SyncE jitter attenuating clock | 0.3 | 2.5; 3.3 | 2.5; 3.3 | QFN36 | 6x6 | |||
| 2 | 2 | 0.008 | 710 | 0.008 | 346 | LVPECL; LVDS; CML; LVCMOS | SyncE jitter attenuating clock | 0.3 | 2.5; 3.3 | 2.5; 3.3 | QFN36 | 6x6 | |||
| 4 | 5 | 19 | 707 | 19 | 1050 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.6 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN36 | 6x6 | |||
| 4 | 5 | 8 | 707 | 0.008 | 1050 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | TQFP100 | 14x14 | |||
| 4 | 5 | 2 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | TQFP100 | 14x14 | |||
| 4 | 5 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | TQFP100 | 14x14 | |||
| 4 | 5 | 2 | 710 | 0.002 | 346 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | TQFP100 | 14x14 | |||
| 4 | 5 | 2 | 710 | 0.002 | 1417 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.3 | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | TQFP100 | 14x14 | |||
| 8 | 8 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.4 | 1.8; 2.5 | 1.8; 2.5 | BGA80 | 10x10 | |||
| 4 | 4 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.4 | 1.8; 2.5 | 1.8; 2.5 | BGA80 | 10x10 | |||
| 8 | 8 | 2 | 710 | 0.002 | 808 | LVPECL; LVDS; CML; LVCMOS | Any-frequency jitter attenuating clock | 0.4 | 1.8; 2.5 | 1.8; 2.5 | BGA80 | 10x10 |
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Si5328 SyncE Jitter Attenuating Clock Multiplier Evaluation Kit
Silicon Labs' Si5328 is the industry’s lowest jitter, most frequency flexible Synchronous Ethernet (SyncE) clock, making it ideal for Ethernet PHYs from GbE to 100 GbE. The Si5328 meets all of the jitter, wander, and holdover requirements specified by ITU-T G.8262/Y.1362.
Si5328 SyncE Jitter Attenuating Clock Multiplier Evaluation Kit
Silicon Labs' Si5328 is the industry’s lowest jitter, most frequency flexible Synchronous Ethernet (SyncE) clock, making it ideal for Ethernet PHYs from GbE to 100 GbE. The Si5328 meets all of the jitter, wander, and holdover requirements specified by ITU-T G.8262/Y.1362.
MSRP $250.00