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Si5325A

General Purpose Jitter Attenuators

The Si5325A jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 2 input(s), 2 output(s) and has a maximum frequency output of 1417 MHz. The Si5325A delivers 0.6 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

 
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Output Frequency Max (MHz)

Key Specs

 
Reference Inputs
2
Clock Outputs
2
Phase Jitter (ps)
0.6
Input Frequency Min (MHz)
10
Input Frequency Max (MHz)
710
Output Frequency Min (MHz)
0.002
Output Frequency Max (MHz)
1417
Output Format(s)
LVPECL; LVDS; CML; LVCMOS
Jitter Attenuator
Yes
PCI Express
No
Package
QFN36
Package Size (mm)
6x6
Reference Inputs
2
Clock Outputs
2
Phase Jitter (ps)
0.6
Input Frequency Min (MHz)
10
Input Frequency Max (MHz)
710
Output Frequency Min (MHz)
0.002
Output Frequency Max (MHz)
1417
Output Format(s)
LVPECL; LVDS; CML; LVCMOS
Jitter Attenuator
Yes
PCI Express
No
Package
QFN36
Package Size (mm)
6x6
jitter-attenuator-BD.png
Find quality, environmental, shipping, and supply chain information for Silicon Labs devices. You can also download the following environmental documents for each part number: Detailed Device Composition (MDDS), IPC 1752-2 Class 6 (XML format), RoHS Certificate of Compliance, ICP test reports, Halogen-Free Certificate of Compliance, PFOS/PFOA Certificate of Compliance, and REACH Declaration.
Company Name Silicon Laboratories, Inc.
Company Address 400 W. Cesar Chavez Austin, TX 78701
Date of Incorporation 1996
Terms and Conditions View PDF
California SB 657 View PDF
Corp Social Responsibility 1996

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