Si538x Wireless Clock Jitter Attenuator, Jitter Cleaner

Si538x wireless clock generators leverage our fourth generation wireless DSPLL® technology to address form factor, power and performance requirements demanded by radio area network equipment, including macrocells, small cells, remote radio heads (RRH) and distributed antenna systems (DAS).  With unparalleled integration, Si538x generators reduce power and size without compromising the stringent performance and reliability demanded in wireless applications. Si538x is the industry’s first wireless clock generator capable of replacing discrete high-performance VCXO-based clocks with a fully integrated CMOS IC solution. Si538x devices are capable of generating both wireless clocks with less than 100 fs typical phase jitter and low jitter general purpose clocks.

Output frequency range
Up to 3 GHz
Phase jitter (RMS)
72 fs

Wireless Jitter Attenuator Common Specs

  • Digital frequency synthesis eliminates external VCXO and analog filter components
  • Jitter performance < 100 fs RMS typ (12 kHz - 20 MHz)
  • 1, 2, and 4 DSPLL options
  • Input frequency range:
    • Differential: 10 MHz - 750 MHz
    • LVCMOS: 10 MHz - 250 MHz
  • Cost effective oscillator
  • Selectable loop bandwidth
  • Status monitoring: LOL, LOS, OOF
  • In-circuit programmable vial SPI and I²C
  • Output frequency range:
    • Wireless DSPLL: 480 kHz - 2.94912 GHz
    • Any-rate DSPL: 1 kHz - 712.5 MHz
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Part Number Customize Input Frequency Output Format(s) DSPLLs Number of Inputs Phase Jitter (RMS) 4G/LTE Wireless Clocks Output Frequency Max Description VDD (V) VDDO (V) Package Type Package Size (mm) Number of Outputs
Customize 0.008 750 CML; HCSL; LVCMOS; LVDS; LVPECL 1 4 0.065 2949.12 Ultra-low phase noise, wireless jitter attenuating clock multiplier 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 12
Customize 0.008 750 CML; HCSL; LVCMOS; LVDS; LVPECL 4 4 0.065 2949.12 Ultra-low phase noise, dual-PLL wireless jitter attenuating clock multiplier 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 12
Customize 0.008 750 CML; HCSL; LVCMOS; LVDS; LVPECL 2 4 0.065 2949.12 Ultra-low phase noise, multi-PLL wireless jitter attenuating clock multiplier 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 12
Customize 0.008 750 CML; HCSL; LVCMOS; LVDS; LVPECL 1 4 0.065 2949.12 Ultra-low phase noise, wireless jitter attenuating clock multiplier 1.8; 2.5; 3.3 1.8; 2.5; 3.3 QFN64 9x9 12

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