Wireless Jitter Attenuator Common Specs
- Digital frequency synthesis eliminates external VCXO and analog filter components
- Jitter performance < 100 fs RMS typ (12 kHz - 20 MHz)
- 1, 2, and 4 DSPLL options
- Input frequency range:
- Differential: 10 MHz - 750 MHz
- LVCMOS: 10 MHz - 250 MHz
- Cost effective oscillator
- Selectable loop bandwidth
Find the Right Wireless Clock Jitter Attenuator
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Part Number | Customize | Input Frequency | Output Format(s) | DSPLLs | Number of Inputs | Phase Jitter (RMS) | 4G/LTE Wireless Clocks | Output Frequency Max | Description | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Number of Outputs |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Customize | 0.008 750 | CML; HCSL; LVCMOS; LVDS; LVPECL | 1 | 4 | 0.065 | 2949.12 | Ultra-low phase noise, wireless jitter attenuating clock multiplier | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 12 | ||
Customize | 0.008 750 | CML; HCSL; LVCMOS; LVDS; LVPECL | 4 | 4 | 0.065 | 2949.12 | Ultra-low phase noise, dual-PLL wireless jitter attenuating clock multiplier | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 12 | ||
Customize | 0.008 750 | CML; HCSL; LVCMOS; LVDS; LVPECL | 2 | 4 | 0.065 | 2949.12 | Ultra-low phase noise, multi-PLL wireless jitter attenuating clock multiplier | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 12 | ||
Customize | 0.008 750 | CML; HCSL; LVCMOS; LVDS; LVPECL | 1 | 4 | 0.065 | 2949.12 | Ultra-low phase noise, wireless jitter attenuating clock multiplier | 1.8; 2.5; 3.3 | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 12 |
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Si5386 Wireless Jitter Attenuating Clock Multiplier Development Kit
The Si5386A-E-EVB makes it easy to move from ClockBuilder Pro device configuration to hands-on performance evaluation.

Si5386 Wireless Jitter Attenuating Clock Multiplier Development Kit
The Si5386A-E-EVB makes it easy to move from ClockBuilder Pro device configuration to hands-on performance evaluation.