Part Number | Customize | Input Frequency Min | Input Frequency Max | Output Frequency Max | Output Format(s) | Loop Bandwidth Min (Hz) | Loop Bandwidth Max (Hz) | Description | Control | Reference Inputs | Clock Outputs | Phase Jitter (RMS) | VDD (V) | VDDO (V) | Package Type | Package Size (mm) | Clock Generators | Jitter Attenuating Clocks | Synchronous Ethernet/1588 | PCI Express Clocks | 4G/LTE Wireless Clocks | Intel x86 Clocks | Output Frequency Min |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Customize | 0.008 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | Network synchronizer and jitter attenuator | I2C/SPI | 5 | 7 | 0.125 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 0.000001 | |||||||
Customize | 0.008 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | Network synchronizer and jitter attenuator | I2C/SPI | 5 | 7 | 0.125 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | QFN64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | 3-PLL network synchronizer with 1PPS in/out | I2C | 5 | 7 | 0.15 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | LGA56 | 8x8 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | 3-PLL network synchronizer with 1PPS in/out | I2C | 5 | 7 | 0.15 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | LGA56 | 8x8 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | 1-PLL network synchronizer with 1PPS in/out | I2C | 5 | 7 | 0.15 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | LGA56 | 8x8 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 4000 | 1-PLL network synchronizer with 1PPS in/out | I2C | 5 | 7 | 0.15 | 1.8 + 3.3V | 1.8; 2.5; 3.3 | LGA56 | 8x8 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 2-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 1.8 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 2-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 1.8 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 2-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 3.3 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 2-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 3.3 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 3-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 1.8 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 3-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 1.8 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 718.5 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 3-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 3.3 | LGA64 | 9x9 | 0.000001 | |||||||
Customize | 0.000001 | 750 | 350 | CML; HCSL; LVCMOS; LVDS; LVPECL | 0.001 | 0.004 | 3-PLL Network Synchronizer clock for IEEE 1588v2 | SPI | 5 | 8 | 0.105 | 1.8 + 3.3 | 3.3 | LGA64 | 9x9 | 0.000001 |
Silicon Labs Timing Solution for Xilinx Zynq® Ultrascale+™ MPSoC and RFSoC
The Xilinx® portfolio of Zynq® Ultrascale+™ MPSoC and RFSoC are families of scalable high-performance FPGA’s combined with System-On-Chip product variants allowing customers to address a wide range of applications and system requirements. The Zynq® family of devices utilize innovative technology to deliver lower total power consumption without sacrificing performance.
Xilinx choose Silicon Labs timing devices to support their MPSoC (ZCU102) and RFSoC (ZCU111) evaluation kits due to their flexibility and low jitter/phase noise enabling their customers to achieve industry leading performance with low power consumption.
Visit Xilinx® MPSoC and RFSoC pages to learn more
Silicon Labs Timing Key Features for Xilinx Designs