Device/Module image

Si5321

SONET Clocks

The Si5321 SONET clock has a jitter of 0.3 ps RMS (OC-192/STM-64) and is part of the SONET/SDH clock multiplier and jitter attenuator family, providing the industry’s best performance in the smallest footprint. The device outperforms discrete implementations and hybrid clock solutions while integrating features such as selectable forward error correction (FEC), frequency scaling, pin-selectable loop filter bandwidths and MTIE-compliant hitless switching. Based on our DSPLL® technology, this clock provides a fully integrated PLL eliminating the need for sensitive external loop filter components and costly VCXOs.

 

Key Specs

 
Reference Inputs
1
Clock Outputs
1
Phase Jitter (ps)
0.3
Input Frequency Min (MHz)
19
Input Frequency Max (MHz)
622
Output Frequency Min (MHz)
19
Output Frequency Max (MHz)
2488
Output Format(s)
CML
Jitter Attenuator
Yes
PCI Express
No
Package Type
PBGA63
Package Size (mm)
9x9
Reference Inputs
1
Clock Outputs
1
Phase Jitter (ps)
0.3
Input Frequency Min (MHz)
19
Input Frequency Max (MHz)
622
Output Frequency Min (MHz)
19
Output Frequency Max (MHz)
2488
Output Format(s)
CML
Jitter Attenuator
Yes
PCI Express
No
Package Type
PBGA63
Package Size (mm)
9x9
sonet-clocks-BD.png
Find quality, environmental, shipping, and supply chain information for Silicon Labs devices. You can also download the following environmental documents for each part number: Detailed Device Composition (MDDS), IPC 1752-2 Class 6 (XML format), RoHS Certificate of Compliance, ICP test reports, Halogen-Free Certificate of Compliance, PFOS/PFOA Certificate of Compliance, and REACH Declaration.
Company Name Silicon Laboratories, Inc.
Company Address 400 W. Cesar Chavez Austin, TX 78701
Date of Incorporation 1996
Terms and Conditions View PDF
California SB 657 View PDF
Corp Social Responsibility 1996

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