How Ethernet is Driving the Need for New Data Center and Wireless Infrastructure Timing Solutions



Since IEEE 802.3 was first published in 1980, Ethernet has come a longway. Ethernet has gradually evolved from a technology envisioned toconnect PCs and workstations to become the networking technology ofchoice for a broad range of applications across enterprise computing, datacenter, wireless networks, telecommunications and industrial.

Due to the ubiquity of Ethernet and the ever-decreasing cost of thehardware needed to support it, Ethernet is poised to continue gainingpopularity in these applications. Some of the most interesting technologytransformations are currently underway as 100G Ethernet is being adoptedin data centers and wireless radio access networks. These migrations tohigh-speed optical Ethernet are driving the need for higher performanceclock and frequency control products.



Data Centers

Traditional enterprise workloads are quickly migrating to public cloud infrastructure, driving a tremendous investmentboom in data centers worldwide. In addition to increasing demands for lower latency, data centers share a uniquechallenge in that the majority of data center traffic stays within the data center as workload processing is distributedacross multiple compute nodes. Modern data centers are optimizing their network architecture to support distributed,virtualized computing by connecting every switch to each other, a trend known as hyperscale computing. One of theunderlying technologies that makes hyperscale computing commercially attractive is high-speed Ethernet. As the data in Figure 1 shows, data center switches are quickly migrating to 25G, 50G and 100G Ethernet to accelerate datatransfer and network efficiency.

The migration from 10G to 25/50/100G Ethernet is driving data center equipment manufacturers to upgrade switchand access ports to higher speeds. This in turn fuels the need for higher performance, lower jitter timing solutions.Ultra-low jitter clocks and oscillators are necessary in these applications because high clock noise can result inunacceptably high bit-error rates or lost traffic. Table 1 highlights the typical timing requirements for Ethernet PHYs,switches and switch fabrics. The safe and proven approach for high-speed Ethernet is to use an ultra-low jitter clocksource that delivers excellent jitter margin to these specifications.

10GbE
25GbE/40GbE
100GbE
1 ps RMS (12 kHz – 20 MHz)
0.3 ps RMS (12 kHz – 20 MHz)
0.15 ps RMS (12 kHz – 20 MHz)

Wireless Radio Access Networks

Wireless networks are poised to go through tremendous change as they migrate from 4G/LTE to LTE-Advanced and5G over the next several years. Next-generation wireless networks will be optimized for carrying mobile data. As shown in Figure 2, mobile data traffic is expected to grow to 49 exabytes per month by 2021, a sevenfold increaseover 2016. To support this exponential increase in demand for bandwidth, wireless networks are being re-architectedand optimized for data transport. The widescale adoption of high-speed Ethernet in radio access networks (RAN) isexpected to be a critical part of this technology advancement.

In 4G/LTE radio access networks, the RF and baseband processing functions performed by base stations are splitinto separate remote radio heads (RRH) and base band units (BBU). As shown in Figure 3, each RRH is connectedto a BBU over a dedicated fiber connection based on the Common Public Radio Interface (CPRI) protocol. Thisarchitecture enables the replacement of dedicated copper and coax cable connections between the radio transceiver(typically located in the cell tower) and the base station (typically located at the ground nearby). This distributedarchitecture enables the BBU to be placed in a more convenient location to simplify deployment and maintenance.While more efficient than legacy 3G wireless networks, this network architecture is limited because the bandwidth isconstrained by the speed of the CPRI link (typically 1 Gbps to 10 Gbps). In addition, the CPRI connection is a pointpointlink and RRH and BBUs are typically deployed in close proximity to each other (<2 km to 20 km), constrainingthe flexibility of network deployments.

As part of the evolution to 5G, the wireless industry is re-thinking base station architectures. The connection betweenbaseband and radio elements, known as the fronthaul network, is a key area for optimization. Higher bandwidthfronthaul networks are required to support new LTE features that support high-speed mobile data, including CarrierAggregration and Massive MIMO. In addition, network densification and the adoption of small cells, pico cells andmicro cells will put additional bandwidth requirements on fronthaul networks. To minimize capex and opex, 5G willuse a Cloud-RAN (C-RAN) architecture that centralizes baseband processing (C-BBU) for multiple remote radioheads.

New standards are being developed for fronthaul to support the evolution to C-RAN. IEEE 1904 Access NetworksWorking Group (ANWG) is developing a new Radio over Ethernet (RoE) standard for supporting CPRI encapsulationover Ethernet. This new standard will make it possible to aggregate CPRI traffic from multiple RRHs and small cellsover a single RoE link, improving fronthaul network utilization. Another working group, IEEE 1914.1 Next GenerationFronthaul Interface (NGFI), is revisiting the Layer-1 partitioning between RF and baseband to support more Layer-1processing at the RRH. NGFI enables the fronthaul interface to move from a point-to-point connection to a multipointto-multipoint topology, improving network flexibility and enabling better coordination between cell sites. A new CPRIstandard for 5G front-haul (eCPRI) will be released in August 2017 that details the new functional partitioning of basestation functions and includes support for CPRI over Ethernet.



As part of the evolution to 5G, the wireless industry is re-thinking base station architectures.



These new fronthaul standards create the need for frequency flexible timing solutions that can support both LTE andEthernet clocking in radio heads, small cells, and pico cells, as shown in Figure 4. These new solutions provide theopportunity for hardware designs to unify all clock synthesis into a single, small-form factor IC.

Another key challenge is accurate timing and synchronization. Historically 3G and LTE-FDD mobile networks reliedon frequency synchronization to synchronize all network elements to a very precise and accurate primary reference,typically sourced from a signal transmitted by GNSS satellite systems (GPS, BeiDou). These systems requirefrequency accuracy within 50 ppb at the radio interface and 16 ppb at the base station interface to the backhaulnetwork. LTE-TDD and LTE-Advanced retain these frequency accuracy requirements but add very stringent phasesynchronization requirements (+/-1.5 us). This is a key requirement to enable new features such as enhanced intercellinterference coordination (eCIC) and coordinated multipoint (CoMP), which maximize signal quality and spectralefficiency. These phase synchronization requirements are expected to be further tightened in the upcoming 5Gstandards.


Figure 5 shows the LTE-Advanced network architecture, in which multiple remote radio heads connected to acentralized base band unit over packet-based eCPRI networks and phase/frequency synchronization is provided byIEEE 1588v2/SyncE. Time and phase synchronization is supported by implementing IEEE1588/SyncE at the remoteradio head and centralized base band unit. Higher bandwidth 100 GbE networks are used to backhaul traffic fromeach base band unit to the core network. Higher performance, more flexible timing solutions are now available thatsimplify clock generation, distribution, and synchronization in LTE-Advanced applications.

Summary

Ethernet is being broadly adopted in data center and wireless networks to enable higher network utilization and lowercost data transmission and to enable new service provider features and services. The transition to packet-basedEthernet networks in these infrastructure applications is driving the need for more flexible, lower jitter timing solutions.Leading timing device vendors are meeting this market need with high-performance clock and oscillator devicesbased on innovative architectures that enable the utmost in frequency flexibility and ultra-low jitter.

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