Hardware design isn’t easy. With the growing number of standards to support and the exponential growth in the complexities that come with high-performance applications, developers are wrestling with striking the right balance between the ever-expanding number of standards, protocols, and specifications as well as incorporating higher speed serial data transmission.
This challenges in the areas of wireless infrastructure, networking, data center, broadcast video, test and measurement, and industrial automation are also impacting timing component selection, since clock jitter can negatively impact the bit-error rate in high-speed serial data transmission applications and the signal-to-noise ratio and effective number of bits in data converter applications. Given the importance of timing, some hardware developers and architects are making clocking decisions at the beginning of the design process rather than waiting until later.
Every hardware design requires some level of timing solution. Depending on application requirements, solutions can range from simple quartz-based crystals and oscillators to more highly integrated clock devices. No one-size-fits-all strategy applies when it comes to component selection. One common question is how to decide when to use an oscillator versus a clock. There are pros and cons with each approach. Another equally challenging question is how do you pick the right clock device for a given application?
Every hardware design requires some level of timing solution. Depending on application requirements, solutions
can range from simple quartz-based crystals and oscillators to more highly integrated clock devices.
The best way to start is to list all system-level clocking requirements by number of clocks, frequency and signal format (for ex, differential versus single-ended). For performance-critical clocking for data converters, Ethernet switches and PHYs, and FPGA transceivers, it’s important to understand each clock’s phase noise or jitter specification. Armed with this information, you can use a simple checklist to help pinpoint the right device for your application.
The simplest clock generation source is an oscillator (XO), which generates a single output clock. In general, it’s best to select an XO when the system only requires one or two clocking references. XO selection criteria should be based on the desired frequency, jitter budget of the downstream device and parts-per-million (ppm) stability. If space and performance are a concern, another increasingly important criterion is power supply noise rejection. Traditional quartz-based oscillators often require a low-dropout (LDO) regulator off-chip to provide a clean supply and a low jitter clock. In switched-mode supply applications, it is beneficial to use PLL-based oscillators that integrate power conditioning on-chip, thereby eliminating the discrete LDO. Another consideration is PCB layout. In some designs, it is preferable to generate all clocks locally, next to the downstream SoC/FPGA/ASIC/PHY. This approach optimizes the transmission line and signal integrity and eliminates the need to route clocks across a densely packed board. Lastly, don’t forget lead times.
The lead time for traditional custom frequency oscillators can approach 14 weeks or longer. Another benefit of PLL-based oscillators is they are available with much shorter lead times (1 week or less).
As a general rule of thumb, a clock device is preferable to an oscillator when the application requires three or more clock references and the target IC’s are all on the same board. A simple clock fanout buffer can be used if all the required clocks are at the same frequency and signal format (single-ended or differential). A PLL-based clock generator should be used if the application requires multiple frequencies and/or signal formats. In many FPGA/ASIC applications, the device has multiple time domains for the data path, control plane and memory controller. These applications are a great fit for a clock generator. Most clock generator applications are free-running, in which the internal PLL and it’s associated output clocks are synchronized to a quartz crystal or XO input. Example free-running applications include clocking for processors, memory controllers, SoCs and peripheral components (e.g. PCI Express, USB).
Some applications require synchronous clocking to ensure the source and destination operate at the same frequency. For synchronous applications, a jitter attenuating clock is recommended to lock to the reference clock, attenuate jitter on the clock signal to remove unwanted noise and provide a low jitter output clock to the downstream device. The jitter filtering function is implemented using a narrowband PLL within the clock IC. These jitter cleaners are often used in wired and wireless infrastructure applications, as well as in broadcast video applications that require multiple cameras and video sources to remain properly synchronized within a television studio.
There are multiple advantages to using an integrated clock device rather than multiple crystal oscillators. Designs can be simplified by replacing multiple potential points of failure in the system with a single device, thereby increasing overall board-level reliability. Also, there are also cost advantages in replacing multiple components with a single IC. However, there are some tradeoffs that must be considered. A centralized clock device that performs all clock generation still requires that all signals get routed and distributed across the board. Best practices for optimizing signal integrity should be used, like routing clocks differentially to take advantage of differential clocks’ common mode rejection. Another consideration is multi-sourcing. XOs are available in industry-standard packages and pinouts, while clock devices are often single-sourced. If multi-sourcing is a concern, a XO-based solution is recommended.
There are multiple advantages to using an integrated clock device rather than multiple crystal oscillators.
High performance clock devices are available that simplify XO replacement by providing any combination of integer and fractional clock synthesis. One important design consideration is to carefully review the fractional clock jitter performance of each device. Some solutions suffer from highly variable fractional clock jitter, risking the device may not provide sufficient jitter design margin in performance-sensitive applications. It is always a safe bet to ask the timing supplier to provide a jitter measurement for performance-critical clocks to ensure the device can satisfy the application requirement. All output clocks should be configured so that the jitter measurement considers crosstalk between output clocks. Another key design consideration is spread spectrum clocking, which is a common technique used to reduce electromagnetic interference (EMI) in computing and industrial applications. If the application requires a mix of spread and non-spread clocks, it is important to review each clock datasheet carefully to ensure the device can simultaneously generate both spread spectrum clocks and square wave clocks.
Integrated clock devices offer further advantages that are useful in some applications. For example, the frequency of each output clock can be changed on some clock devices, simplifying frequency margining testing during design verification. The phase of each output clock can similarly be changed on some clock devices, making it easy to line up clock output edges and to compensate for PCB-level trace length mismatch between clock signals. While these features aren’t always required, it provides peace-of-mind knowing they are supported in case they are needed to optimize a design.
The table below summarizes the selection criteria that should be considered when making clocking decisions on your next design.
|Parameter||XO||Clock Buffer||Clock Generator||Jitter Attenuator|
|# output clocks||1||2+||2+||2+|
|Board routing flexibility||Easy||More complex||More complex||More complex|
|Frequency diversity||Single frequency||Single frequency||Multiple frequency||Multiple frequency|
|Clock output signal format (single-ended or differential)||Ordering option||Ordering option or pin-strap|
|Board-level reliability||Depends on number of timing components. In general, the fewer the number of components, the higher the board-level reliability.|
|Multi-sourceFeatures that simplify clock tree design||Small form factor||Low additive jitter||Integer + fractional clock synthesis||Integer + fractional clock synthesis|
|Placement next to IC||Format/Level translation (some devices)||Format/Level translation||Format/Level translation|
|Built-in power supply noise rejection||Jitter cleaning|
Picking the right clock or oscillator for an upcoming design can be greatly simplified by following the guidelines listed above. Silicon Laboratories offers a broad range of jitter attenuating clocks, clock generators, clock buffers, XOs, and VCXOs to meet customers’ unique timing requirements. More information about these products is available at www.silabs.com/timing.
Please select at least one column.