Power Supply Rejection Ratio (PSRR) in Low Jitter Clocks and Oscillators
Power delivery and noise coupling concerns as it relates to PSRR are as critical as ever in electronic system design. While increasing power supply decoupling and careful power plane design with good isolation between ICs can help reduce this type of noise, cost, feature and design constraints may limit the designer’s ability to fully leverage these techniques. To compound the issue, systems that require the best jitter performance also typically have the greatest amount of power supply noise.
Impact of Power Supply Noise and PSRR in Timing Devices
although there are system solutions to power supply noise, the best remedy is to use timing components that reject external noise. Silicon Labs’ novel timing devices use cutting edge-techniques to provide ultra-low jitter that is minimally affected by power supply noise.
Silicon Labs’ DSPLL® technology, based on a patented digital control algorithm, enables all the functionality that traditional analog PLLs provide but with precise digital control. Using digital circuitry that includes a digital low-noise variable oscillator instead of an analog VCO reduces sensitivity to analog influences. Furthermore, on-chip, low-noise regulators enhance isolation from power rail noise. The result is a low-jitter technology that can be used in very noisy environments.
Additive Jitter of Traditional XOs is three times to ten times greater than DSPLL-based XOs